Thesis 3b6f18

CHAPTER 1 INTRODUCTION & LITERATURE REVIEW

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CHAPTER 1

INTRODUCTION & LITERATURE REVIEW

Limited fossil fuel reserves and ever increasing population are posing a challenging issue of catering the increasing demand of electrical energy. At the same time, environmental issues such as global warming are also a cause of serious concern to humanity. In response to these problems, most countries have adopted policies which broadly cover two directives: 

Efficient utilization of current energy resources.



Finding out ways for effective utilization of renewable energy resources. The conversion of power from one form to another is a major part of the utilization

process. Hence, an efficient and effective conversion process is needed to reduce the waste of energy and improve the power quality. 1.1 INTRODUCTION Power electronics has emerged as a key technology in achieving the aforesaid. It involves application of solid state electronics for the conversion and control of electric power in a wide range (mill watts to hundreds of megawatts). Power electronic converters can be found anywhere wherever there is need to modify a form of electrical energy (i.e. change its current, voltage or frequency). These can be classified according to the type of input and output power. 

AC to DC (rectifier)



DC to AC (inverters)



DC to DC (DC-to-DC converter)



AC to AC (AC-to-AC converter) Among the various power electronic converter system listed above, inverters play a

crucial role in utilization of renewable energy resources. Renewable energy systems like Photovoltaic (PV) or Fuel Cell (FC) and Wind Turbine (WT) systems employ power inverters to generate AC voltage of desired magnitude and frequency for grid connection. Going by the need of high efficiency and power quality in these systems, the development of high performance inverters is the major focus of today‘s power electronic industry [1]. 1.1.1 TWO-LEVEL VOLTAGE SOURCE INVERTER Switch-mode dc-to-ac inverters used in ac power supplies and ac motor drives where the objective is to produce a sinusoidal ac output whose magnitude and frequency can both be controlled. Practically, we use an inverter in both single-phase and three phase ac systems. A 2

half-bridge is the simplest topology, which is used to produce a two level square-wave output waveform. A center-tapped voltage source supply is needed in such a topology. It may be possible to use a simple supply with two well-matched capacitors in series to provide the center tap. The full-bridge topology is used to synthesize a three-level square-wave output waveform. The half-bridge and full-bridge configurations of the single-phase voltage source inverter are shown in Fig. 1.1 and 1.2 respectively. In a single-phase half-bridge inverter, only two switches are needed. To avoid shootthrough fault, both switches are never turned on at the same time. S1 is turned on and S2 is turned off to give a load voltage, VAO in Fig. 1.1, of +V S/2. To complete one cycle, S1 is turned off and S2 is turned on to give a load voltage, VAO, of -VS/2. In full bridge configuration, turning on S1 and S4 and turning off S2 and S3 give a voltage of VS between point A and B (VAB) in Fig. 1.2, while turning off S1 and S4 and turning on S2 and S3 give a voltage of VS.

Fig. 1.1 Half-bridge configurations

Fig. 1.2 Full-bridge configurations.

To generate zero level in a full-bridge inverter, the combination can be S1 and S2 on while S3 and S4 off or vice versa. The three possible levels referring to above discussion are shown in Table 1.1. Note that S1 and S3 should not be closed at the same time, nor should S 2 and S4. Otherwise, a short circuit would exist across the dc source. The output waveform of half & full-bridge of single-phase voltage source inverter are shown in Fig.1.3& 1.4, respectively

TABLE 1.1 LOAD VOLTAGES WITH CORRESPONDING CONDUCTING SWITCHES.

Conducting Switches

Load Voltage VAB

S1 , S 4

+VS

S2 , S 3

-VS

S1,S2 or S3, S4

0

3

Fig. 1.3 Half-bridge configuration.

Fig. 1.4 Full-bridge configuration

Limitations of 2-level inverters .

Two-level inverter configuration has following limitations if employed in high voltage

and high power applications:  In high power applications, the problems associated with commutations (e.g. power dissipation of the order of 1-2 kW in each semiconductor) cause the switching frequency not to reach very high values. Because of high switching losses and snubber losses, it has relatively poor efficiency.  Due to limited switching frequency, high current and torque harmonics are produced which limited the maximum speed achievable. Hence, compromise is to be made between lowest possible switching frequency and lowest possible harmonics.  Common mode voltage generated across inverter and motor terminals is more which plays an important role in determining the control technique and switching frequency of inverter. It affects the bearing life of the machine.  The blocking voltage rating and current rating of the devices has to be increased. 1.1.2 CONCEPT OF MULTI LEVEL INVERTERS Multilevel converters are power conversion systems of composed by an array of power semiconductors and capacitive voltage sources that, when properly connected and controlled, can generate a multi-step voltage waveform with variable and controlled frequency, phase and amplitude. The stepped waveform is synthesized by selecting different voltage levels generated by the proper connection of the load to the different capacitive voltage sources. This connection is performed by the proper switching of the power semiconductors. The number of levels of a converter can be defined as the number of steps or constant voltage values that can be generated by the converter between the output terminal and any

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arbitrary internal reference node within the converter. Typically, it is a dc-link node, and it is usually denoted by N and called neutral. To be called a multilevel converter, each phase of the converter has to generate at least three different voltage levels. This differentiates the classic two-level voltage source converter (2L-VSC) from the multilevel family. Some singlephase examples of this concept and their respective waveforms are given Fig.1.5 for different number of levels. It is worth mention that, generally different voltage levels are equidistant from each other in multiples of Vdc. Two-level converters can generate a variable frequency and amplitude voltage waveform by adjusting a time average of their two voltage levels. This is usually performed with pulse-width modulation (PWM) techniques [35]. On the other side, multilevel converters add a new degree of freedom, allowing the use of voltage levels as an additional control element and giving more alternatives to generate the output waveform. For this reason, multilevel inverters have intrinsically improved power quality, characterized by: lower voltage distortion (more sinusoidal waveforms), reduce dv/dt, and lower common-mode voltages, which reduce or even eliminate the need of output filters.

Fig. 1.5 2-level and 3 –level Inverters & output wave forms Disadvantages of 2- level Inverters Therefore, the reasons for moving towards multilevel from 2-level concept are listed below:  Large dv/dt and di/dt ratings of switches.  Static and dynamic voltage sharing problem among devices when connected in series/parallel, to achieve high voltage and high power capabilities from the same ratings of available devices.  Switching frequency is very high resulting more switching losses and reduced overall efficiency. 5

 Switches must have very low turn-on and turn-off times for high power applications due to very high switching frequencies.  Higher order harmonics have been introduced, and  Large common mode voltages have been generated across industrial motor phases, which results in premature motor bearing failures and shaft leakage currents. Because of these shortcomings of conventional two-level inverters, recent trend is now switching towards more number of voltage levels at inverter terminals. Multilevel inverters are mainly used to achieve high voltage and high power capabilities with reduced harmonic contents. Power quality is also one issue considered by researchers working in the field. Main source of power quality problem, i.e. harmonic distortion, can be reduced by using filter circuits or by employing appropriate pulse width modulation (PWM) technique within inverter/converter. Filters have to carry large current from inverter, increasing its cost and size. Therefore, PWM techniques are used in such a manner so that dominant low order harmonics get suppressed resulting in minimal requirement of filtering (to eliminate only some of the higher order harmonics). It reduces cost and rating of the filters. Increased switching frequency can be used to reduce harmonic contents. But it is limited by switching loss constraint. Therefore, switching frequency cannot be increased beyond certain limit. To achieve high voltage, high power output from conventional two-level inverter, series/parallel connections of switching devices are required. Due to series connection, voltage levels across each device may differ and during switching intervals the rate of change of voltages and voltage sharing among devices will be difficult. In parallel connection of switching devices, current sharing during switching intervals may create unbalancing problem across load and through devices. Thus dynamic voltage and current sharing is difficult in series/parallel connections of switching devices in two-level inverters. Because of above limitations and shortcomings of conventional 2-level inverters, need arose to develop an alternative which can produce high voltage, high power output efficiently with improved power quality. After significant research around the world, now a day‘s multilevel inverters have been found better counterpart to the conventional two-level inverters in medium and high voltage applications. 1.1.3 MULTILEVEL INVERTERS FEATURES, ADVANTAGES & APPLICATIONS The elementary concept of multilevel inverter involves the use of a number of power semiconductor switches with several lower voltage DC source to synthesize a stepped AC

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waveform at the output which is closer to a sinusoid. Using this concept, Nabae et al in 1981 proposed a new three-level inverter topology which was called ―neutral-point-clamped PWM inverter (NPC-PWM)‖ [10]. This topology had the potential to be extended to N-levels. Features of Multi-Level Inverters Multilevel inverters have a number of advantages over the conventional two-level high switching frequency PWM inverter [2-7]. Some of these are listed below. 1. less switching stress on devices 2. high voltage & high power capability 3. reduced harmonic contents without increasing switching frequency or decreasing the inverter power output 4. no need of extending the device rating 5. reduced switching losses 6. reduced dv/dt 7. reduced (or even eliminated) common mode voltages 8. good electromagnetic compatibility (EMC) 9. elimination of the problem of unequal device ratings 10. Capacitor voltage balancing along with significant reduction in Device Count. Limitations of Multi-Level Inverters Multilevel inverters do have some disadvantages also [57]. Some of them in particular are listed below: 

Requirement of large number of power semiconductor switches.



Related gate drive circuit for each switch causing the overall system to be expensive and complicated.

Power electronic researchers have put in continuous efforts in developing topologies which retain the inherent benefits of multilevel inverters with lesser number of power switches and other additional features. With the advent of new topologies, a greater stress is also put on to investigate new switching methods. This is due to the fact that a particular switching strategy for a given topology can result in improvement of harmonic profile of output waveform as well as reduction in switching and conduction power losses. The three switching methods most discussed in the literature are [15]: 

Carrier-based PWM



Selective Harmonic Elimination

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

Space-vector PWM



Optimized Harmonic PWM (OHPWM)

Applications of Multi-Level Inverters Multilevel converters are considered today as a very attractive solution for mediumvoltage high-power applications. In fact, several major manufacturers commercialize NPC, FC, or CHB topologies with a wide variety of control methods, each one strongly depending on the application. Particularly, the NPC has found an important market in more conventional high-power ac motor drive applications like conveyors, pumps, fans, and mills, among others, which offer solutions for industries including oil and gas, metals, power, mining, water, marine, and chemistry [26], [27]. The back-to-back configuration for regenerative applications has also been a major plus of this topology, used, for example, in regenerative conveyors for the mining industry [28] or grid interfacing of renewable energy sources like wind power [29], [30]. On the other hand, FC converters have found particular applications for high bandwidth–high switching frequency applications such as medium-voltage traction drives [31]. Finally the cascaded H-bridge has been successfully commercialized for very high-power and power-quality demanding applications up to a range of 31 MVA, due to its series expansion capability. This topology has also been reported for active filter and reactive power compensation applications [32], electric and hybrid vehicles [33], [34], photovoltaic power conversion [35]–[37], uninterruptible power supplies [38], and magnetic resonance imaging [39].

Fig. 1.6 Applications of Multi level inverters

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1.2 INTRUDUCTION TO TMS320C28335 The F2833x (C28x+FPU) family is a member of the TMS320C2000™ digital signal controller (DSC) platform. The C28x+FPU based controllers have the same 32-bit fixed-point architecture as TI's existing C28x DSCs, but also include a single-precision (32-bit) IEEE 754 floating-point unit (FPU). It is a very efficient C/C++ engine, enabling s to develop their system control software in a high-level language. It also enables math algorithms to be developed using C/C++. The device is as efficient at DSP math tasks as it is at system control tasks that typically are handled by microcontroller devices. This efficiency removes the need for a second processor in many systems.

1.2.1 1INTRODUCTION TO THE U The 32 x 32-bit MAC 64-bit processing capabilities enable the controller to handle higher numerical resolution problems efficiently. Add to this the fast interrupt response with automatic context save of critical s, resulting in a device that is capable of servicing many asynchronous events with minimal latency. The device has an 8-leveldeep protected pipeline with pipelined memory accesses. This pipelining enables it to execute at high speeds without resorting to expensive high-speed memories. Special branch-look-ahead hardware minimizes the latency for conditional discontinuities. Special store conditional operations further improve performance. This device draws from the best features of digital signal processing; reduced instruction set computing (RISC); and microcontroller architectures, firmware, and tool sets. The U features include a modified Harvard architecture and circular addressing. The RISC features are single-cycle instruction execution, -to- operations, and modified Harvard architecture (usable in Von Neumann mode). The microcontroller features include ease of use through an intuitive instruction set, byte packing and unpacking, and bit manipulation. The modified Harvard architecture of the U enables instruction and data fetches to be performed in parallel. The U can read instructions and data while it writes data simultaneously to maintain the single-cycle instruction operation across the pipeline.

1.2.2 OVERVIEW OF DSPF28335 The Micro-28335 is a standalone development platform that enables to evaluate and develop applications. Micro – 28335 have a wide range of Application environments. Key features of Micro-28335 include

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

A Texas Instruments TMS320F28335 device with a Digital Signal Controller and can be operated up to 150 MHz frequency



On chip SARAM (34K x 16)



On chip Flash (256K x 16)



8K x 16 Boot ROM



USB to RS-232 Interface



Configurable boot load options



16 LEDs/2 Limit Switch



Single voltage power supply (+5V)



Expansion connectors for SPI/GPIO termination.



Embedded JTAG Emulation



14 Pin TI JTAG Interface



20x4 Normal LCD / 128x64 Graphical LCD Interface



LD JTAG Interface



16 Channel ADC



4 Channel Parallel DAC/8 Channel Serial DAC

1.2.3 COMPONENTS OF THE U As shown in Fig. 1.7 the U contains: 

A U for generating data- and program-memory addresses; decoding and executing instructions; performing arithmetic, logical, and shift operations; and controlling data transfers among U s, data memory, and program memory

Fig. 1.7 High-Level Conceptual Diagram of the U 10



Emulation logic for monitoring and controlling various parts and functionalities of the DSP and for testing device operation



Signals for interfacing with memory and peripherals, clocking and controlling the U and the emulation logic, showing the status of the U and the emulation logic, and using interrupts

1.2.4 MEMORY INTERFACE The C28x memory map is accessible outside the U by the memory interface, which connects the U logic to memories, peripherals, or other interfaces. The memory interface includes separate buses for program space and data space. This means an instruction can be fetched from program memory while data memory is being accessed. The interface also includes signals that indicate the type of read or write being requested by the U. These signals can select a specified memory block or peripheral for a given bus transaction. Memory Bus (Harvard Bus Architecture) As with many DSC type devices, multiple busses are used to move data between the memories and peripherals and the U. The C28x memory bus architecture contains a program read bus, data read bus and data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read and write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable single cycle 32-bit operations. The multiple bus architecture, commonly termed Harvard Bus, enables the C28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and memories attached to the memory bus will prioritize memory accesses. Generally, the priority of memory bus accesses can be summarized as follows: 

Data Writes (Simultaneous data and program writes cannot occur on the memory bus)



Program Writes (Simultaneous data and program writes cannot occur on the memory bus)



Data Reads Program (Simultaneous program reads and fetches cannot occur on the Reads memory bus)



Fetches (Simultaneous program reads and fetches cannot occur on the memory bus)

Address and Data Buses The memory interface has three address buses: Program address bus (PAB): The PAB carries addresses for reads and writes from program space. PAB is a 22-bit bus.

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Data-read address bus (DRAB): The 32-bit DRAB carries addresses for reads from data space. Data-write address bus (DWAB): The 32-bit DWAB carries addresses for writes to data space. The memory interface also has three data buses: Program-read data bus (PRDB): The PRDB carries instructions or data during reads from program space. PRDB is a 32-bit bus. Data-read data bus (DRDB): The DRDB carries data during reads from data space. PRDB is a 32-bit bus. Data-/Program-write data bus (DWDB): The 32-bit DWDB carries data during writes to data space or program space. TABLE 1.2 BUS USE DURING DATA-SPACE AND PROGRAM-SPACE ACCESSES

Address type Read for program space Read for data space Write to program space Write to data space

Address Bus

Data Bus

PAB

PRDB

DRAB

DRDB

PAB

DWDB

DWAB

DWDB

1.2.5 POWER SUPPLY: The Micro-28335 operates from a single +5V external power supply connected to the main power input (P1). Internally, the +5V input is converted into core voltage, +1.8V,+3.0V and +3.3V using Texas Instruments ADP333x Power Management Unit. The +3.3V and +1.8V and +3.0V supply are used for the DSP's I/O Buffers and other chips on the board. +3.0V supply is used for ADC section.

1.2.6 PERIPHERALS The F28335 device s the following peripherals which are used for embedded control and communication: ePWM:The PWM peripheral s independent/complementary PWM generation, adjustable

dead-band generation for leading/trailing edges, latched/cycle-by-cycle

trip mechanism. Some of the PWM pins HRPWM features. eCAP: The capture peripheral uses a 32-bit time base and s up to four programmable events in continuous/one-shot capture modes. This peripheral can also be configured to generate an auxiliary PWM signal.

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eQEP: The QEP peripheral uses a 32-bit position counter, s low-speed measurement using capture unit and high-speed measurement using a 32-bit unit timer. This peripheral has a watchdog timer to detect motor booth and input error detection logic to identify simultaneous edge transition in QEP signals. ADC: The ADC block is a 12-bit converter, single ended, 16-channels. It contains two sample-and hold units for simultaneous sampling.

1.3 LITERATURE REVIEW Multilevel inverters are now well known to power industries and have tremendous capabilities at medium and high voltage applications. Various aspects of multilevel inverters are researched and reported in the literature. Some of these aspects are Multilevel Inverter Topologies/Design of Modular Structure, and Modulation Techniques. The modulation techniques employed for 2-level inverters can be applied for MLI such as SPWM, OHSW and SHEPWM etc with appropriate modifications. There are so many reports and research paper available in the field of MLI. For my thesis purpose I have chosen some of research paper. These are follows.

A complete survey and comparison of different PWM techniques for 2-level voltage source inverter is presented by Holtz J. [14]. These PWM techniques includes feed-forward schemes (i.e. SPWM, SVPWM, optimized PWM, optical sub-cycle PWM etc.) and schemes (i.e. hysteresis current control, sub-oscillation current control, predictive current control, trajectory tracking control etc.). Several performance criteria are used to find suitable PWM technique for particular applications. Different multilevel inverter control techniques have been compared in [15, 13, 16] on the basis of THD, distortion factor, fundamental and rms line voltages.

To achieve accurate controller output performance, the dynamic model of the system is necessary. Steinke Jurgen k.,[17] described the basic principle of generating the control signals for three-level diode clamped inverter using SPWM technique. It explains switching frequency optimal PWM with NPP control to obtain balanced output voltage across inverter. Analysis of SPWM control technique for induction motor drives to compare voltage harmonics, stator harmonic losses, rotor harmonic losses, loss factor has been presented.

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The type of modulation technique to be used in various applications can be determined by the modulation index of the system. For low modulation index levels, threephase modulation achieves the best results while for high modulation index levels, singlephase modulation achieves the better results by Sadaba O. Alonoso, Sanchis p., Taberna J. Lopez, and Palomo l. marroyo. [18]. It also explains the relationship between voltage THD and phase shift between carriers. Velaerts presented several PWM techniques with analytical expressions of loss factor for 3-level inverter in each case. It shows that sub harmonic dipolar PWM technique can eliminate a specific harmonic band. Transition from dipolar mode to optimized five angles for cycle mode gives better performance in of THD and loss factor.

Sinusoidal PWM, Space Vector PWM and SHEPWM techniques are commonly used for multilevel inverter control. A very useful PWM technique to eliminate specific lower order harmonics was proposed first time by Bhagwat in 1983. Sirisukprasert Siriroj [19] presented the optimized PWM technique that switches the main power devices only once per cycle with wide range of modulation indexes. The basic concept is to swap the polarity of some levels to achieve low modulation index. For 7-level cascaded inverter, the lowest modulation index achievable is 0.1 against 0.5 in traditional techniques.

The important problem in SHEPWM technique is to solve the non-linear transcendental equations for accurately obtaining the notch angles so that fundamental voltage will be generated without producing specific higher order harmonics. Several techniques to solve these equations have been reported in the literature. Tolbert Leon M. [20] have suggested that transcendental equations can be converted into transcendental equations which are solved by using method of resultants from elimination theory [19]. Tolbert presented a technique based on method of resultants using elimination theory. If the no of DC source is very large for increased levels in the inverter output voltage, the degree of polynomials is quite large resulting in computational burden of their resultant polynomials by elimination theory. Thus, Tolbert reformulated the problem in of power systems which reduces the degree of polynomial equations that must be solved significantly and reduces the computational burden.

The very basic operating principle of SVPWM for two level inverters was presented by Holtz J [14] for induction motor control. The main drawback of SVPWM technique is its 14

complex implementation. Wang Fei and McGrath Brendan Peter [21, 22] presented a simple SVPWM technique for three-level inverter which is based on two-level SVPWM technique. The problems of determining sector location and calculating the dwelling times have been much simplified by using co-ordinate transformations. However the redundancy control and complexity in implementation still remains. The co-relation between SPWM and SVWM techniques is required to appropriate design the offset signal to be added to match the performance of SPWM with SVPWM technique.

In MLI the redundant vectors are more than that in 2-level inverter, so the inverter performance can be much improved. The inherent relations between two technique is given in[21] which uses common mode injections in SPWM technique and dwell time calculations in SVPWM for equivalence. But this work employed constant time ratio of Active redundancies.

Another reported work on co-relationship between SPWM and SVPWM techniques is found from Nho N.V. [23] in which a theoretical analysis of these two techniques for the entire modulation index range is presented. Among several methods the minimum common mode PWM method can attain a proper balancing of switching losses besides NPP control. Variable off-set voltage generates various voltage profiles for NPC inverter.

A review and comparison has been made for DCMI, FCMI and Cascaded MLI by Newton C. and Summer M. [29, 30]. It is also described the basic operation of these three topologies in a very nice manner. Use of multi-pulse rectifiers at input side of the inverter can improve the supply as well as load side performance. A very good tour on multilevel inverters can be seen in [31, 32]. These papers give different topologies, control techniques and applications of multilevel inverters. Topologies without and with regenerative front end converters and back-to-back connection of multilevel converters are also presented. At high power levels, the common mode voltage level and distance between controller and power module is large which can produce additional noise and upset the system. So, a future trend is to use fiber optic technologies for sensors, gate drive controllers and communications. Due to availability of advanced optimization tools such as genetic algorithm (GA) and particle swarm optimization (PSO) etc, the problem of solving the non-linear transcendental equations have been rectified up to some extent. Genetic algorithm does not need extensive derivations and analytical expressions. GA is a search method to find the maximum of 15

functions by mimicking the biological evolutionary processes by Ozpineci Burak, [33]. A GA technique is presented to multilevel inverter to determine the optimum switching angles for 7-level cascaded MLI for eliminating some higher order harmonics while maintaining the same fundamental voltage. A comparison between SHEPWM and single carrier SPWM technique is presented in [34] by Dahidah Mohammad S. A., which gives equivalence between these two methods.

1.4 RESEARCH OBJECTIVE This work aims to investigate an inverter topology as an alternative to two stage DCAC converter system in renewable energy systems with the help of multilevel inverters. Both the single-phase and three-phase cases are discussed. The proposed system consists of a switched-capacitor circuit in combination with an Neutral point clamped inverter. The objective of the thesis is as follows: 1)

Simulink implementation of NPC-MLI for a 3-level using Single pulse width modulation.

2)

Simullink implementation of NPC-MLI inverter for 3 level & 5 levels using SPWM.

3)

compare the results of the multilevel inverter for single pulse width modulation and SPWM various levels.

4) Hardware implementation of single pulse width modulated NPC-MLI for a 3 level using DSPf28335

1.5 METHODOLOGY The Methodology for implementation of the Neutral point Multi Level Inverter can be achieved by the following steps. 1. Simulink Implementation: Implement the Proposed model of NPC in MATLAB/SIMULINK environment. The implementation consists of the following steps a. Connect the MOSFET switches in the proposed model. b. Generate the Gate control signals by any of the control strategies suitable for the NPC inverter. c. Design the parameters of protection circuits for the switches. d. To connect a DC supply for the NPC e. Check results for the 3-Level and 5-Level

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2. Hard Ware Implementation: Generation of Gate control signals in DSP28335 by following procedure. a. Write the ‗C‘ code for PWM signal generation. b. By using Code Compose Studio convert the ‗C‘ code to the Assembly Language. c. load all the source files, library files and command files into the DSP 28335. d. Check the PWM output at PWM port. e. Give the generated Gate control signals to the respective switches of the NPC-MLI.

1.6 OUTLINE OF THESIS Second chapter of this dissertation deals with a brief overview of different multilevel inverter topologies and new research topics in this field are presented their advantages and disadvantages are discussed briefly and these topologies are compared in different aspects. And deals with the various modulation techniques that can be employed for the control of multilevel inverters. Focus is made on the carrier based PWM methods wherein the PWM methods based on both the variation of carrier signal and variation of reference signal are discussed. These methods are then compared in of overall THD and the presence of lower order harmonics. In chapter 3, the Neutral point clamped multilevel inverter topology is introduced. Given the analysis of 3-level topology and derived the output voltage and output current. Discussing the inverter operation and gate signal generation. Simulation results and discussions are covered in chapter 4 for a 3-level 1 phase and 3-level 3 phase neutral point clamped inverter with different modulation schemes compare their voltage THD with 5 level inverter. Hardware implementation of Neutral point clamped is discussed in chapter 5 in addition with a working processor, Epwm module description of DSP28335. The experimental results of NPC- MLI with R & RL- load are analysed. Chapter 6 presents the conclusion, various issues associated with the proposed system and future works that can be done on this topology are covered.

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CHAPTER 2 MULTILEVEL INVERTER TOPOLOGIES & MODULATION TECHNIQUES

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CHAPTER 2

MULTILEVEL INVERTER TOPOLOGIES & MODULATION TECHNIQUES

As mentioned in the previous chapter, multilevel inverters utilize an array of power switches and several lower voltage DC sources to generate a stepped output voltage waveform with variable and controllable frequency, phase and amplitude. Batteries, capacitors and renewable energy resources can be used as multiple DC voltage sources.

2.1 MULTILEVEL INVERTER TOPOLOGIES Multilevel inverters are recognized by their stepped output waveform. The generalized stepped waveform for a single-phase N-level multilevel inverter is shown in Fig. 2.1. The waveform is composed of equal positive and negative halves of (N-1)/2 voltage levels wherein a sine wave can be approximated as shown. Usually the number of levels, N in the output is odd instead of even. This is because of inclusion of zero voltage level which makes the stepped output waveform sinusoidal and improves its harmonic profile. Vo (N-1)/2 2Vdc Vdc 0

Ө1 Ө2

Өn

t

-Vdc -2Vdc -(N-1)/2

Fig. 2.1 Generalized stepped waveform of multilevel inverters In the generalized waveform, Ө1, Ө2……..Өn are the switching angles. Both the widths and heights of the steps can be adjusted. However, heights of the steps are generally made equal and only widths are adjusted according to the desired waveform shape by varying the switching angles. For a three-phase system, the levels of one phase are combined with those of the other phases, generating more different levels in the line-to-line voltage. For a converter with N P 19

phase to neutral voltage levels, NL = 2N-1 levels can be found in the line-to-line voltage (a zero-level is redundant). Something similar happens in the three-phase load voltage, where combinations of the line voltages are produced, obtaining NLoad = 2NL-1 voltage levels. However, only NP is used to refer to the number of levels of the converter, since these are the levels generated by the converter independently of the number of phases or the load connection type [4].

2.1.1 CLASSIFICATION OF MULTILEVEL INVERTERS As shown in Fig. 2.2, the classification of multilevel inverters is done on the basis of three topologies, the diode-clamped multilevel inverter (DCMLI), the flying-capacitor multilevel inverter (FCMLI) and the cascaded H-bridge multilevel inverter (CHBMLI) [2-4, 6]. These topologies can also be termed as classical topologies as a number of new configurations are derived from them.

Fig. 2.2 Multilevel inverter classifications 2.1.1.1 DIODE-CLAMPED MULTILEVEL INVERTER Diode-clamped multilevel inverter is the name given to neutral-point clamped PWM inverter extended to higher number of levels [3, 4]. The diode-clamped multilevel inverter has found wide acceptance for its capability of high voltage and high efficiency operation. Fig.

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2.3 shows the power circuit of a 5-level diode-clamped inverter. For clarity of the figure, only one phase is shown. It requires four complementary pairs of switch (S1, S1′), (S2, S2′), (S3, S3′) and (S4, S4′) which are defined such that turning ON one pair of switch prohibits other switch pairs to get activated. For a 5-level inverter, a set of four switches are ON at any given time. C1, C2, C3 and C4 are DC-link capacitors which sustain equal voltage. If they are being fed by a DC link voltage of Vdc, the capacitors voltages will be Vdc/4. Clamping diodes are used to limit the voltage stress across the power switch to one capacitor voltage level. For increasing number of levels in the output, the number of clamping diodes increases quadratically with number of output levels although this quadratic increase in number of clamping diodes is justified so that each diode has the same rating as the active switches. S1 Vdc /4

C1 S2

S3 Vdc /4

C2 S4

Vdc

a

n

Va , S1

Vdc /4

C3 ,

S2

,

S3 Vdc /4

C4 ,

S4

Fig. 2.3 3-level Diode-clamped inverter

Fig. 2.4 5-level Diode-clamped inverter

TABLE 2.1 SWITCHING PATTERN OF DIODE-CLAMPED MULTILEVEL INVERTER

Output VAO V5 = Vdc V4 = 3dc/4 V3= Vdc/2 V2 = Vdc/4 V1=0

Sa1 1 0 0 0 0

Sa2 1 1 0 0 0

Sa3 1 1 1 0 0

Switch State Sa4 Sa'1 1 0 1 1 1 1 1 1 0 1

21

Sa'2 0 0 1 1 1

Sa'3 0 0 0 1 1

Sa'4 0 0 0 0 1

Table 2.1 presents switching pattern of a 5-level diode-clamped inverter. State

―1‖

indicates that the switch is ON and state ―0‖ indicates that the switch is OFF. It is obvious from this table that in each cycle just four switches should be ON. It is evident from the table that a diode-clamped multilevel inverter does not possess phase redundancies. Instead it has only line-line redundancies [2, 7] From the application point of view, multilevel diode-clamped inverter can act as an interface between a high-voltage dc transmission line and an ac transmission line [2]. Another application would be as a variable speed drive for high-power medium-voltage (2.4 kV to 13.8 kV) motors as proposed in [2, 7, 18, 19]. Static var compensation is an additional function for which several authors have proposed for the diode-clamped converter. The advantages and disadvantages of diode-clamped multilevel inverter are listed below [2, 3, 4, 6]. Advantages: 

All the phases share a common DC bus, which minimizes the capacitance requirement of the inverter.



Capacitors can be pre-charged as a group.



Efficient is high for fundamental frequency switching.

Disadvantages: 

Voltage sharing between the DC-link capacitors becomes an issue as the number of output levels increases.



Real power flow is difficult for a single inverter.



Requirement of large number of clamping diodes for number of output levels greater than 3.

Due to above disadvantages, the industrial acceptance of diode-clamped inverter is limited to three levels only [4].

2.1.1.2 FLYING-CAPACITOR MULTILEVEL INVERTER Fig. 2.5 shows one phase leg of the power circuit for a flying-capacitor 5-level inverter. The whole configuration is similar to diode-clamped topology, except for the fact that instead of using clamping diodes, capacitors Ca, Cb and Cc are used in their place. These capacitors are called flying capacitors. The voltage on each capacitor differs from that of the next capacitor. The voltage increment between two adjacent capacitor legs gives the size of the voltage steps in the output waveform. Table 2.4 shows the switching pattern of a 5-level

22

flying-capacitor multilevel inverter. It can be observed that the flying-capacitor inverter does not require all of the switches that are active to be in a consecutive series as in a diodeclamped inverter. As evident from Table 2.2, flying-capacitor multilevel inverter possesses phase redundancies. In other words, there can be more than a single switching combination to generate the same voltage level. These redundancies can be incorporated in the control strategy which ultimately helps in regulating the voltage across the dc-link capacitors. The main advantages and disadvantages of flying-capacitor multilevel inverter are listed below [2, 3, 4, 6]. S1 Vdc /4

C1 S2 Cc S3

Vdc /4

Cb

C2

S4 Vdc

Cc

n

Ca

a

Va ,

S1 Vdc /4

C3

Cb ,

S2

Cc ,

S3 Vdc /4

C4 ,

S4

Fig. 2.5 A 3-level flying capacitor inverter

Fig. 2.6 A 5-level flying capacitor inverter

TABLE 2.2 SWITCHING PATTERN OF FLYING CAPACITOR MULTILEVEL INVERTER

Output VAO V5 = Vdc V4 = 3Vdc/4 V3= Vdc/2 V2 = Vdc/4 V1=0

Sa1 1 1 1 1 0

Sa2 1 1 1 0 0

Sam-1 1 1 0 0 0

Switch State Sam Sa'1 Sa'2 1 1 0 0 1 0 0 1 1 0 1 1 0 1 1

Sa'm-1 0 0 0 1 1

Advantages: 

Phase redundancies help in balancing the voltage across the capacitors.



Ability to ride through short duration outages and deep voltage sags.

23

Sa'm 0 0 0 0 1



Real and reactive power flow can be controlled.

Disadvantages: 

Large number of capacitors is required which makes the overall system to be expansive and bulky.



Complex control strategy is needed to track the voltage across all the capacitors. Also pre charging of all the capacitors to the same voltage level thus making the start up process complicated.



Switching utilization and efficiency are poor for real power transmission.

2.2.1.3 CASCADED H-BRIDGE MULTILEVEL INVERTER As discussed earlier, a full bridge is called an H-bridge inverter because of its resemblance with the alphabet ‗H‘. While a full bridge inverter generates a three level output, series connection of N such bridges can produce 2N+1 levels in the output. This series connection is known as cascaded H-bridge multilevel inverter [12]. A 5-level cascaded Hbridge inverter is shown in Fig. 2.7. The functioning of a single H-bridge is similar to that explained in section 2.1. Each H-bridge requires an isolated dc source/capacitor to generate its corresponding output. The switches are activated in such a way that the output voltage across the load terminals is the aggregation of the voltage generated by all the H-bridges. The switching pattern for a 5-level inverter is shown in Table 2.3. It can be observed that cascaded H-bridge topology presents more redundancies than the previous topologies, since each H-bridge or has one redundant switching state and the series connection inherently introduces more redundancies.

S1a

S1b

Vdc

Va1

,

S1a

,

S1b

Vo

S2a

S2b

Vdc

Va2

,

S2a

Fig. 2.7 A H-bridge inverter

,

S 2b

Fig. 2.8 A 5-level cascaded H-bridge inverter

24

TABLE 2.3 SWITCHING PATTERN OF CASCADED H-BRIDGE MULTILEVEL INVERTER

Output VAO V5 = Vdc V4 = 2Vdc V3=- Vdc V2 =-2 Vdc V1=0

Sa1 1 1 0 0 1

Sa2 0 0 1 1 1

Sa3 1 1 1 0 1

Switch State Sa4 Sa'1 Sa'2 1 0 1 0 0 1 1 1 0 1 1 0 1 0 0

Sa'3 0 0 0 1 0

Sa'4 0 1 0 0 0

Due to its structure and modularity, it has been proposed for such applications as static var generation, an interface with renewable energy sources, and for battery-based applications. Three-phase cascaded inverters can be connected in wye or in delta. Peng has demonstrated a prototype multilevel cascaded static var generator connected in parallel with the electrical system that could supply or draw reactive current from an electrical system [2225]. Peng [23] and Joos [26] have also shown that a cascade inverter can be directly connected in series with the electrical system for static var compensation. Cascaded inverters are ideal for connecting renewable energy sources with an ac grid, because of the need for separate dc sources, which is the case in applications such as photovoltaic or fuel cells. Cascaded inverters have also been proposed for use as the main traction drive in electric vehicles, where several batteries or ultra capacitors are well suited to serve as separate DC sources [27, 28]. The cascaded inverter could also serve as a rectifier/charger for the batteries of an electric vehicle while the vehicle was connected to an ac supply. Additionally, the cascade inverter can act as a rectifier in a vehicle that uses regenerative braking. Major advantages and disadvantages of cascaded H-bridge inverter are listed below [2, 3, 4, 6]. Advantages: 

The number of possible output voltage levels is more than twice the number of dc sources.



The series of H-bridges makes for modularized layout and packaging. This will enable the manufacturing process to be done more quickly and cheaply.

Disadvantages: 

Isolated dc sources are required for each H-bridge. This will limit its application to areas where there is availability of multiple dc sources.

25

2.1.1.4 ASYMMETRIC MULTILEVEL INVERTER The multilevel inverter configurations discussed so far come under the category of symmetric multilevel inverter as the DC-link capacitors sustain equal voltage. One interesting alternative is to have different capacitor voltages. This topology of inverters is known as asymmetric multilevel inverter. Although the focus for this kind has been mainly addressed in the direction of cascaded H-bridge topology [15-17, 29] asymmetric multilevel inverter can also be derived from diode-clamped and flying-capacitor multilevel inverters or a combination of them either [16, 17]. Asymmetric multilevel inverters have the same circuit configuration as symmetric ones. The only difference is the dc link capacitor voltages. Using different dc link voltages in different power cells and application of the appropriate switching methods, the number of output voltage levels increases. Therefore, with less number of switches, more output voltage levels can be obtained, in the symmetric inverter, 16 switches are needed to generate 9-level voltage, whereas in the asymmetric inverter, 8 switches are enough to generate the same number of voltage levels. The number of output voltage levels in an asymmetric multilevel inverter is calculated by the following equation 𝑘

𝑁=2

𝑉𝑑𝑖 + 1

(2.1)

𝑖=1

where k denotes the number of DC voltage sources and Vdi denotes the normalized dc voltage of each cell with respect to the dc link capacitor voltage. Thus for the asymmetric configuration shown in Fig. 2.10, the number of output voltage levels is 2(1+3)+1 = 9. Although the number of power switches and associated gate driver circuits are reduce greatly in asymmetric multilevel inverters, this may lead to following compromises and challenges: 

Increased power rating of switches



Increased number of input sources



Loss of modularity



Reduced number of redundant states



Complex modulation/control schemes



Difficulty in possibility of charge balance control (especially in open loop mode)

26

2.2 COMPARISON BETWEEN MULTILEVEL INVERTER TOPOLOGIES The comparison between classical multilevel inverter topologies is shown with the help of table 2.4. Comparison is made on the basis of different components required to realize a 5-level and N-level topology. It can be observed that the total number of components required in realizing a 5-level topology is less for cascaded H-bridge inverter. Based on the requirement for a 5-level inverter, the function for total component count can be derived for N-levels in the output. The plot of these functions for N = 5 to 31 is shown in Fig. 2.9. While the graph for diode-clamped and flying-capacitor inverter follows a parabolic path, the graph for cascaded H-bridge increases linearly. Thus it can be inferred that for higher number of output levels, component requirement for a cascaded H-bridge inverter is way less than the other two topologies. For exceeding higher number of levels in the output, the realization of diode-clamped and flying-capacitor inverter becomes impractical. TABLE 2.4 COMPARITIVE ANALYSES OF CLASSICAL MULTILEVEL INVERTERS

Diode

Flying

Cascaded

Clamped

Capacitor

H-Bridge

Output voltage Levels

5

N

5

N

5

N

Clamping Diodes

12

(N-1)(N-2)

0

0

0

0

Floating Capacitors

0

0

6

(N-1)(N-2)/2

0

0

(N-1)

4

(N-1)

2

(N-1)/2

8

2(N-1)

8

2(N-1)

18

(N2+3N-4)/2

10

5(N-1)/2

Topology

DC-link Capacitors/Isolated 4 supplies Main Switches(with diodes)

8

Total component count

24

2(N-1) N2-1

1000 Diode Clamped Flying Capcitor Cascaded H-Bridge

Number of compenets required

900 800 700 600 500 400 300 200 100 0

5

10

15

20 Number of levels

25

Fig. 2.9 Number of components required for classical multilevel inverter topologies

27

30

2.3 MODULATION TECHNIQUES Modulation is the process in which the power switches of a power electronic converter are controlled to switch from one state to another. Modulation techniques for inverters are required to overcome input voltage changes and meet the need of voltage/frequency control. With the advent of multilevel inverters, power electronic researchers focused on extending the conventional two-level modulation to multilevel case. While it gave rise to increased complexity in order to control more power switches, more flexibility was provided by the additional switching states generated by these topologies. As a result, a large number of schemes have been developed and adapted depending upon the application and inverter topology, each having unique merit and demerit. Fig. 2.10 depicts the classification of the modulation schemes on the basis of the average switching frequency with which multilevel inverters operate. Methods that operate with high switching frequency have many commutations of the power switches per cycle of the fundamental output voltage while the low switching frequency methods generally have one or two commutations in one cycle of the fundamental output voltage. It should be noted here that for high power applications, high switching frequency refers to frequency more than 1 kHz [4]. Multilevel Modulation

Low Switching Frequency

Selective Harmonic Elimination

High Switching Frequency

Hybrid Modulation

Multicarrier PWM

Space Vector Modulation

Fig. 2.10 Classification of multilevel modulation methods As discussed earlier, the three modulation schemes most discussed in the literature are: 

Carrier based PWM: This method includes the comparison of a reference sinusoidal signal with triangular carrier signals which are modified either horizontally or vertically to reduce the harmonic content in the output.



Selective Harmonic Elimination (SHE): It is a low switching frequency method in which a few (generally from three to seven) switching angles per quarter fundamental cycle are predefined and pre-calculated via Fourier analysis to ensure the elimination of undesired low order harmonics [enabling tech paper].



Space Vector PWM (SVM): The space vector modulation (SVM) algorithm is basically also a PWM strategy with the difference that the switching times are 28

computed based on the three-phase space vector representation of the reference and the inverter switching states rather than the per-phase in time representation of the reference and the output levels. Hybrid modulation is a method which basically works on both low and high switching frequency. It is used for the modulation of CHB inverter with asymmetric configuration. The main purpose is to reduce the switching losses of the power switches present in higher power cells. Therefore, instead of using high frequency carrier-based PWM methods in all the cells, the high-power cells are operated with square waveform patterns, switched at low frequency, while only the small power cell is controlled with unipolar PWM [4]. Due to simplicity and popularity of carrier based PWM; this method is analyzed in detail in this chapter and will be applied for modulation in the proposed work.

2.3.1 CARRIER BASED PWM In this section, first fundamentals of 2-level PWM and its characteristics will be explained. Based on these characteristics, this method will be extended for its application in multilevel inverters. For all of inverters (2-level or multilevel) minimum and maximum values of the carrier and reference signals and the corresponding output voltages will be normalized to -1 and +1 with respect to the input dc voltage. 2-level PWM Fig. 2.11 shows 2-level PWM fundamentals. In this figure a reference signal which is usually a sinusoidal waveform, is compared with a carrier signal which is usually a triangular waveform. Based on this figure, if we assume that the average output voltage in switching cycle Ts is Vavg , we have: 𝑇1 𝑉1 + 𝑇2 𝑉2 = 𝑇𝑆 𝑉𝑎𝑣𝑔 And,

𝑇1 + 𝑇2 = 𝑇𝑆 𝑉𝑎𝑣𝑔

(2.2) (2.3)

where T1 is the switching time where the reference signal is lower than the carrier. V1 is the minimum voltage and is generated by subtraction of reference and carrier signals when the reference is lower than carrier. T2 is the switching time where the reference signal is higher than the carrier and V2 is the maximum voltage and is generated by subtraction of reference and carrier signals when the reference is higher than carrier.

29

D1

D2

V2

1

Vavg Reference

Carrier

V1

0 T1

T2 Ts

Fig. 2.11 Basics of 2-level PWM If we solve the above equation for two switching times, T1 and T2 , we have: 𝑇1 =

(𝑉𝑎𝑣𝑔 − 𝑉2 )𝑇𝑠 (𝑉2 − 𝑉1 )

(2.4)

𝑇2 =

(𝑉𝑎𝑣𝑔 − 𝑉1 )𝑇𝑠 (𝑉2 − 𝑉1 )

(2.5)

The equation (2.2) shows a linear relation between switching times and average of output voltage. The previous equations can be rewritten based on duty cycles (Dk), i.e. the ratio of conduction times (Tk) and total switching period (Ts): 𝐷𝑘 =

And

𝑇𝑘 , 𝑘 = 1, 2 𝑇𝑠

(2.6)

𝐷1 𝑉1 + 𝐷2 𝑉2 = 𝑉𝑎𝑣𝑔

(2.7)

𝐷1 + 𝐷2 = 1

(2.8)

From equation (2.5), it can be concluded that duty cycles can be stated as normalized form of average voltages. For example, duty cycle D2 corresponds to average voltage Vavg for mapping [V1, V2] → [0, 1]. Also, according to equation (2.2) switching times can be calculated. In addition, desired output voltage can be compared with a linear ramp wave in the switching period. Thus, if desired voltage is higher than ramp, higher level of output voltage is selected; otherwise lower level is selected. There are different methods to generate modulation signals [40]. All these methods can be presented by similar graphic diagrams: a reference signal is compared to a carrier signal and output state is selected based on which signal is higher at any moment. In selection of carrier and reference signals there are some points which are mentioned below:

30



Carrier signal is usually a symmetric triangular wave, but a saw tooth wave can be used either. Important fact is that the symmetric signal generates fewer harmonic [40].



The reference signal can be continuous or sampled synchronous with carrier signal. The second method usually generates fewer harmonics. Since today digital controllers are used, this method is preferred [42].Fig. 2.12 shows an example of 2-level PWM. 1

0

-1 10

0.002

0.004

0.006

0.008

0.01

0.012

0.014

0.016

0.018

0

-1

Fig. 2.12 Carrier and reference waveform of 2-level PWM

2.3.2 MULTILEVEL OR MULTICARRIER PWM Multilevel PWM is basically a generalization of the 2-level PWM wherein the sinusoidal reference signal is naturally sampled with the help of a number of carrier signals. To be more specific, an N-level multilevel inverter requires N-1 carrier signals to sample the reference signal and generate the switching signals for the power switches incorporated in the inverter topology [41]. These power switches then operate accordingly to produce the required multilevel output. For an N-level inverter, N-1 carriers with the same frequency fc and the same amplitude Ac are disposed such that the bands they occupy are contiguous. The reference waveform has peak-to-peak amplitude Aref, a frequency fref, and its zero centered in the middle of the carrier set. The reference is continuously compared with each of the carrier signals. If the reference is greater than a carrier signal, then the active device corresponding to that carrier is switched on; and if the reference is less than a carrier signal, then the active device corresponding to that carrier is switched off. In multilevel inverters, the amplitude modulation index, ma, and the frequency ratio, mf are defined as 𝑚𝑎 =

𝐴𝑟𝑒𝑓 (𝑁 − 1)𝐴𝑐

(2.9)

31

𝑚𝑓 =

𝑓𝑐 𝑓𝑟𝑒𝑓

(2.10)

A number of varieties of multilevel PWM are present which are mostly based upon the variation of either the carrier or the reference signal. These are shown in the Fig. 2.13 [45, 49] Multilevel PWM

Variation in Reference Signal

Variation in Carrier Signal

Pure Sinusoidal

Level Shifted

Third Harmonic Injection

Phase Shifted

Switching Frequency Optimal

Level and Phase Shifted

Dead Band

Super Imposed Carrier

Other Techniques

Fig. 2.13 Classification of Multilevel PWM 2.3.2.1 Level Shifted PWM (LS-PWM) It is the most basic extension of the 2-level PWM for N-level multilevel inverter wherein instead of one carrier signal, N-1 carrier signals are used which are shifted vertically with respect to each other. Since each carrier is associated to two levels, the same principle of 2-level PWM can be applied, taking into that the control signal has to be directed to the appropriate power switches in order to generate the corresponding levels in the output. A level-shifted PWM can be implemented in three different ways [46, 47, 48, 50]: 

Phase Disposition (PD-PWM): wherein all the carrier signals are in same phase.



Phase Opposition Disposition (POD-PWM): wherein the carrier signals above the zero are out of phase with those below the zero by 180º.



Alternative Phase opposition Disposition (APOD-PWM): wherein the adjacent carrier signals are out of phase by 180º..

32

Examples of these methods for a 5-level inverter are shown in Fig. 2.14 to Fig. 2.16. 1

0

-1 1 0

0.002

0.004

0.006

0.008

0.01

0.012

0.014

0.016

0.018

0

-1

Fig. 2.14 PD-PWM with ma = 0.85 and mf = 40 1

0

-1 1 0

0.002

0.004

0.006

0.008

0.01

0.012

0.014

0.016

0.018

0

-1

Fig. 2.15 POD-PWM with ma = 0.85 and mf = 40 1

0

-1 1 0

0.002

0.004

0.006

0.008

0.01

0.012

0.014

0.016

0.018

0

-1

Fig. 2.16 APOD-PWM with ma = 0.85 and mf = 40 LS-PWM method is especially useful for diode-clamped inverters, since each carrier can be easily associated to two power switches of the inverter. It is generally accepted that LS-PWM gives rise to lesser harmonics distortion for the line-to-line voltage. However, this strategy suffers from unequal device switching frequency and unequal device conduction period which can affect the charging and discharging of the DC link capacitors thus resulting in their unequal loading [48]. Due to this, LSPWM strategy is not suitable for cascaded Hbridge inverter topology 2.3.2.2 Phase Shifted PWM (PS-PWM) In this strategy of modulation, the carrier signals are shifted in phase with respect to each other which are then compared with the reference signal [47, 48, 50]. Similar to LSPWM, N-1 carrier signals which have the same frequency and peak-to-peak amplitude are required for

33

the modulation of an N-level inverter where the phase shift Φs between the adjacent carrier signals is given by, 𝛷𝑆 =

360 ͦ (𝑁 − 1)

(2.11)

𝛷𝑆 =

180 ͦ (𝑁 − 1)

(2.12)

Equation 2.10 and 2.11 are applicable for flying-capacitor and cascaded H-bridge inverter respectively. 1

0

-1 1 0

0.002

0.004

0.006

0.008

0.01

0.012

0.014

0.016

0.018

0

-1

Fig. 2.17 PS-PWM with ma = 0.85 and mf = 40 It should be noted that PSPWM is not applicable for diode-clamped inverter as it does not possess any switching redundancy. However, it is perfectly suitable for CHB and FC inverter topologies as they possess switching redundancies [48, 50]. Also in PS-PWM, switch device usage is evenly distributed which allows for equal loading of DC link capacitors. This method leads to higher distortion in the line voltages compared to LS-PWM. Fig. depicts the phase-shift modulation of a 5-level FC inverter wherein four carrier signals are used. According to the equation (2.10), these carrier signals are shifted in phase by 90º from each other 2.3.2.3 Level and Phase Shifted PWM (LPS-PWM) This technique of modulation incorporates the features of both the LSPWM and PSPWM [43]. Two bands are used for modulation wherein the carrier signals above and below zero have the same peak-to-peak amplitude and frequency with a phase shift in between them. 1

0

-1 1 0

0.002

0.004

0.006

0.008

0.01

0.012

0.014

0.016

0

-1

Fig. 2.18 LPS-PWM with ma = 0.85 and mf = 40 34

0.018

This phase shift depends upon the number of levels in output i.e. 180º for a 5-level inverter, 120º for a seven-level inverter, 90º for a nine-level inverter and so on [45, 46, 49]. With the increase in the number of levels, more carrier signals are included. In general, N-1 carrier signals will be required for an N-level inverter. Fig2.18. shows the LPS-PWM method for a five level inverter. 2.3.2.4 Super Imposed Carrier PWM (SIC-PWM) This technique of modulation uses a single carrier signal which is symmetrical with respect to zero. This carrier signal is then superimposed with the sinusoidal reference signal as shown in the Fig. 2.19. 1 0 -1 1 0

0.002

0.004

0.006

0.008

0.01

0.012

0.014

0.016

0.018

0.002

0.004

0.006

0.008

0.01

0.012

0.014

0.016

0.018

0 -1 1 0 0 -1

Fig. 2.19 Superimposition of a carrier signal with sinusoidal reference signal 1

0

-1 10

0.002

0.004

0.006

0.008

0.01

0.012

0.014

0.016

0.018

0

-1

Fig. 2.20 SIC-PWM and its output The resulting signal is then compared with N-1 DC signals to generate the control signals for the power switches of an N-level inverter. Each DC signal corresponds to the average value of the carrier signals used in PD-PWM method [44, 45, 49]. This is shown in Fig. 2.20. The advantage of this method is that only one carrier signal has to be used which avoids the additional complexity associated with the generation of multiple carrier signals. Also the resulting reference signal is compared with different DC signals which are easier to generate in the binary format. Thus this method can be implemented easily for multilevel inverters to be used in applications like amplifiers [44]. 2.3.2.5 Sinusoidal PWM (SPWM) It is the most widely accepted technique for modulation wherein the reference signal is a sinusoidal signal and it is compared with N-1 carrier signals. However, there are methods other than the SPWM method in which DC link utilization is better in linear modulation

35

region. The DC utilization means the ratio of the output fundamental voltage to the DC link voltage. Methods like THIPWM, SFOPWM, Dead Band control etc. belong to this category. Of various such methods, THIPWM and SFOPWM will be discussed in the next subsection. It should be noted that carrier orientation for these methods can be either level-shifted or phase-shifted. 2.3.2.6 Third Harmonic Injection PWM (THI-PWM) In this method, the sinusoidal reference signal is injected by a third harmonic with a magnitude of 25% of the fundamental [45, 47, 49]. The resulting signal is a flat topped waveform which is shown in Fig. 2.21. 1 0 -1 0

0.002

0.004

0.006

0.008

0.01

0.012

0.014

0.016

0.018

0

0.002

0.004

0.006

0.008

0.01

0.012

0.014

0.016

0.018

0.5 0

1 0 -1

Fig. 2.21 Third harmonic signal superimposed with the reference signal This resultant is then compared with N-1 carrier signals to generate the N-level output. It should be noted that this scheme introduces third harmonic in the line to neutral waveform. However, for a balanced load with floating neutral point, third harmonic current cannot flow and hence third harmonic voltage is absent in line to line waveform. The flat topped waveform allows for over modulation while maintaining excellent ac term and dc term spectra. Thus this scheme acts as an alternative to improve the output voltage without entering the over-modulation range. So any carriers employed for this reference will enhance the output voltage by 15% without increasing the harmonics [47, 57]. 1

0

-1 10

0.002

0.004

0.006

0.008

0.01

0.012

0.014

0

-1

Fig. 2.22 THI-PWM with ma = 1 and mf = 40

36

0.016

0.018

During the dead band interval the power devices of one of the three-phases are not switched. This results in a 33% reduction in the average switching frequency compared to conventional carrier based techniques thereby reducing the associated switching losses. On the other hand, use of this scheme gives rise to larger harmonic losses. The reference curve can not only be superimposed by third harmonic but also by a dc offset

2.4 COMPARISON OF THE MODULATION SCHEMES Table 2.5 presents a comparison between the aforesaid modulation schemes when they are applied for the control of a 5-level inverter. For each case, the carrier frequency is taken 2 kHz whereas frequency of the reference signal is 50 Hz. It can be observed from the table that the THD of 2-level PWM is higher in comparison to the rest of the methods. However, the absence of lower order harmonics is a major advantage over the conventional method of modulation. The higher value of THD is due to the presence of higher order harmonics. Removal of higher order harmonics is done by filters circuits which can be smaller in size than those required for removal of lower order harmonics. This can reduce the size, weight and associated cost of the overall system. TABLE 2.5 COMPARISONS OF MODULATION SCHEMES

7th 9th 5th harmonic harmonic harmonic (%) (%) (%)

Modulation Scheme

THD(%)

3rd harmonic (%)

2-level PWM

133.02

0.03

0.04

0.01

0.04

PD-PWM

35.99

0.00

0.01

0.01

0.01

POD-PWM

35.89

0.30

0.01

0.33

0.20

APOD-PWM

36.09

0.02

0.01

0.01

0.02

PS-PWM

36.15

0.06

0.04

0.02

0.04

LPS-PWM

36.09

0.02

0.02

0.01

0.02

SIC-PWM

26.91

0.01

0.02

0.02

0.01

THI-PWM

32.98

12.51

0.02

0.00

0.02

SFO-PWM

38.04

20.68

0.03

0.01

2.06

37

Table 2.5 also shows that the lower order harmonic profile in PD-PWM, POD-PWM, APOD-PWM, PS-PWM and CSI-PWM method is significantly improved. LPS-PWM incorporates the advantages of both LS-PWM and PS-PWM methods thus allowing for lower THD as well as even distribution of switch device usage. Also the overall THD is quite less than the 2-level PWM method which verifies the advantages of using multicarrier PWM. Modulation schemes like THIPWM and SFOPWM are optimized PWM methods in which the third harmonic content is significantly higher. Thus these methods are used for three-phase systems in which the third harmonic is absent. However, the injection of third harmonic in these optimized PWM methods increases the available linear modulation region to reduce the THD in three-phase systems.

2.5 SUMMARY In this chapter, conventional topologies of multilevel inverters have been investigated. First, different topologies of multilevel inverters, their advantages and disadvantages have been discussed. A comparison has been made between the three major multilevel inverter topologies and it was shown for drives applications implementation of NPC topology is easy. In this chapter classification for multilevel modulation techniques was shown. The focus was then shifted on the carrier based PWM techniques in which the principle of 2-level PWM was discussed. After this, multilevel or multicarrier PWM was discussed under which modulation schemes which are either based on variation of carrier signal or reference signal were covered. A comparison between these modulation schemes was done on the basis of overall THD and presence of lower order harmonics. Finally, the effect of modulation index on the level utilization for a multilevel inverter was discussed.

38

CHAPTER 3 NEUTRAL POINT CLAMPED MULTI- LEVEL INVERTER

39

CHAPTER 3

NEUTRAL POINT CLAMPED MULTI- LEVEL INVERTER

Different multilevel topologies discussed in previous chapter among them neutral point clamped multilevel inverter is easily implemented for 3 phase circuits. For drives applications performance of 3 phase 3 level neutral clamped multi level inverter is better than others. This topology gives the better voltage, current harmonic spectrum for connect the motor drive. 3.1 INRODUCTION The most commonly used multilevel topology is the diode clamped inverter, in which the diode is used as the clamping device to clamp the dc bus voltage so as to achieve steps in the output voltage. Fig. 3.1 shows the circuit for a diode clamped inverter for a three-level and a four-level inverter. The key difference between the two-level inverter and the three-level inverter are the diodes D1 and D2. These two devices clamp the switch voltage to half the level of the dc-bus voltage. In general the voltage across each capacitor for an N level diode clamped inverter at steady state is V dc/n-1. Although each active switching device is only required to block V, the clamping devices have different ratings. The diode-clamped inverter provides multiple voltage levels through connection of the phases to a series of capacitors. According to the original invention, the concept can be extended to any number of levels by increasing the number of capacitors. Early descriptions of this topology were limited to threelevels [4] where two capacitors are connected across the dc bus resulting in one additional level. The additional level was the neutral point of the dc bus, so the terminology neutral point clamped (NPC) inverter was introduced [4]. However, with an even number of voltage levels, the neutral point is not accessible, and the term multiple point clamped (MPC) is sometimes applied [5]. Due to capacitor voltage balancing issues, the diode-clamped inverter implementation has been limited to the three levels. Because of industrial developments over the past several years, the three level inverter is now used extensively in industry applications. 3.2 ANALYSIS OF NPC In general for a N level diode clamped inverter, for each leg 2 (N-1) switching devices, (N-1) * (N-2) clamping diodes and (N-1) dc link capacitors are required. When N is sufficiently high, the number of diodes and the number of switching devices will increase and make the system impracticable to implement. If the inverter runs under pulse width modulation (PWM), the diode reverse recovery of these clamping diodes becomes the major 40

design challenge. Though the structure is more complicated than the two-level inverter, the operation is straightforward and well known [5]. In summary, each phase node (a, b, or c) can be connected to any node in the capacitor bank (V3, V2, V1). Connection of the a-phase to positive node, V3 occurs when S1ap and S2ap are turned on and to the neutral point voltage, When S2ap and S1an are turned on and the negative node V1 is connected when S1an and S2an are turned on. There are some complementary switches and in a practical implementation, some dead time is inserted between the gating signals and their complements meaning that both switches in a complementary pair may be switched off for a small amount of time during a transition. However, for the discussion herein, the dead time will be ignored. From Fig. 3.1, it can be seen that, with this switching state, the a-phase current Ia will flow into the junction through diode D1a if the current is negative or out of the junction through diode D2a if the current is positive. The dc currents I3, I2, and I1 are the node currents of the inverter.

Fig 3.1 Neutral point clamped inverter . A pair of diodes is added in each phase for each of the two junctions. The operation is similar to the three-level. For practical implementation, the switching state needs to be converted into transistor signals. Once the transistor signals are established, general expressions for the a-phase line-to-ground voltage and the a-phase component of the dc currents can be written as Va0=HaNVN0+HaN-1VN-10+.....+Ha1V10

(3.1)

Vb0=HbNVN0+HbN-1VN-10+.....+Hb1V10

(3.2)

Vc0=HcNVN0+HcN-1VN-10+.....+Hc1V10

(3.3)

41

The node current for the N-level inverter are given by IN= HaNIa+HbNIb+HcNIc

(3.4)

IN-1= HaN-1Ia+HbN-1Ib+HcN-1Ic

(3.5)

I1= Ha1Ia+Hb1Ib+Hc1Ic

(3.6)

The above relationships may be programmed into simulation software to form a block that simulates one phase of a diode-clamped inverter. A number of blocks can be connected together for a multiphase system. For more simulation details, the transistor and diode KVL and KCL equations may be implemented. This allows inclusion of the device voltage drops (as well as conduction losses) and also the individual device voltages and currents. To express this relationship, consider the general N-level diode-clamped structure. Therein, only the upper half of the inverter is considered since the lower half contains complementary transistors and may be analyzed in a similar way. Through the clamping action of the diodes, the blocking voltage of each transistor is the corresponding capacitor voltage in the series bank. The inner diodes of the multilevel inverter must block a higher voltage. For example, in the four-level topology the inner diodes must block two-thirds of the dc voltage while the outer diodes block one-third. This is a well-known disadvantage of the diode-clamped topology. For this reason, some authors represent the higher voltage diodes with lower voltage diodes in series [6] or alter the structure of the topology so that each diode blocks the same voltage [7]. Finally, the capacitor junction currents may be expressed as the difference of two clamping diode currents. In case of a three-level inverter, the expression reduces to C1pVc1=-Idc+Ha3Ia+Hb3Ib+Hc3Ic

(3.7)

C1pVc2=-(Idc+Ha1Ia+Hb1Ib+Hc1Ic)

(3.8)

3.3 GATE SIGNAL AND INVERTER OPERATION According to four-switch combination, three output voltage levels, +V, -V, and 0, can be synthesized for the voltage across A and B. During inverter operation shown in Fig. 3.1, switch of S1 and S2 are closed at the same time to provide Vdc/2 a positive value and a current path for I0. Switch S1‘ and S2‘ are turned on to provide V dc/2 a negative value with a path for I0. Depending on the load current angle, the current may flow through the main switch or the freewheeling diodes. When all switches are turned off, the current will flow through the freewheeling diodes. In case of zero level, there are two possible switching patterns to synthesize zero level, for example, 1) S1 and S2 on, S‘1 and S‘2 off, and 2) S1 and S2 off and

42

S‘1 and S‘2 on. A simple gate signal, repeated zero-level patterns, is shown in Fig. 3.2. All zero levels are generated by turning on S1 and S2.

Fig. 3.2 Repeated zero-level switching pattern. Note that level 1 represents the state when the gate is turned on, and level 0 represents the state when the gate is turned off. In Fig. 3.1, S1 and S2 are turned on longer than S‘1 and S‘2 do in each cycle because the same zero level switching pattern is used. As a result, S1 and S2 are consuming more power and getting higher temperature than the other two switches. To avoid such a problem, a different switching pattern for zero level is applied. In the first zero stage, S1 and S2 are turned on; then, in the second zero stage, S‘1 and S‘2 are turned on instead of S1 and S2. By applying this method, turn-on time for each switch turns out to be equal, a shown in Fig. 3.3. +VDC/2

Output waveform

-VDC/2

S1

S2 S’1 S’2

Fig. 3.3 Gate signal pattern 3.4 SUMMARY In this chapter discussed about the neutral point multilevel operation and derived the line voltage and current equations. A 3-level single-phase inverter based on the above topology was presented. Its various operating modes were discussed and comparison was done with conventional multilevel inverter topologies

43

CHAPTER 4 SIMULATION STUDIES

44

CHAPTER 4

SIMULATION STUDIES

In previous chapter discussed the neutral point clamped multi level inverter operation based on that operation to simulate the neutral point clamped inverter by using MATLAB/Simlink with different modulation techniques. The simulation for 3-level single-phase and five-phase inverter is performed using Sim Power electronics toolbox in MATLAB/SIMULINK environment. The simulation model is shown in Fig. 4.1 &. Modulation index M is defined as, 𝑀=

2𝐴𝑟𝑒𝑓 (𝑁 − 1)𝐴𝑐

(4.1)

Fig. 4.1 Three-level Neutral Point Clamped Multilevel Inverter Any of the multicarrier PWM methods discussed in chapter 2 can be applied. However the choice of a particular method depends upon factors like capacitor voltage ripples, input current, output current, output voltage and harmonic profile of the output phase and line voltages. It is clear from Table 2.5 that SIC-PWM gives the best harmonic spectrum among various methods. However, this method when applied to the single-phase configuration causes larger ripples in capacitor voltage thereby causing enhanced flow of input current. This can cause larger conduction losses and hence reduction in efficiency. In view of the

45

aforementioned constraints, PD, APOD, POD&PS-PWM is chosen as the modulation method for both the configurations. 4.1 SINGLE PULSEWIDTH MODULATION The simulink model of a 3 level Neutral point clamped multilevel inverter is shown in the Fig. 4.1. Values of various parameters used in this model are given in Table 4.1. Modulation technique used is Single PWM. To give input DC voltage is 24 volts. DC link divides the given voltage to two equal quantities. The generated gate pulses from single PWM techniques give to respected IGBT. Observe the output wave form on analyser. Fig. 4.2 & Fig 4.3 shows the output line voltage and current with a R load of 91Ω and RL load of 78Ω,36mH whose amplitude is around 12.3 volts which is close to 12 volts. Form the voltage and current Harmonic spectrum observe that single PWM having more %THD because of low modulation index. The %THD of a voltage is 20.53% and current are 30.19% they are shown in the Fig. 4.4& 4.5 respectively. TABLE 4.1 SIMULATION PARAMETERS FOR SINGLE-PHASE INVERTER Parameters

Value

R int and R snubber of IGBT

0.01 Ω, 105 Ω

V dc

24 volts

Load

R = 78 Ω, L = 36 mH

Modulation Index M f carrier

0.85 1 kHz

f ref

50 Hz

Capacitance and R ESR of dc-link

2200µF, 200 mΩ

Fig. 4.2 Line Voltage & Current waveforms of 3-level NPC-MLI with R-load

46

Fig. 4.3 Line Voltage & Current waveforms of 3-level NPC-MLI with RL-load

Fig. 4.4 Harmonic spectrum of Phase voltage

Fig. 4.5 Harmonic spectrum of Phase current

4.2 SINUSOIDAL PULSEWIDTH MODULATION It is the most widely accepted technique for modulation wherein the reference signal is a sinusoidal signal and it is compared with N-1 carrier signals. However, there are methods other than the SPWM method in which DC link utilization is better in linear modulation region. The DC utilization means the ratio of the output fundamental voltage to the DC link voltage. 4.2.1 3-level inverter The simulink model of a 3 level Neutral point clamped multilevel inverter is shown in the Fig. 4.1. Values of various parameters used in this model are given in Table 4.2. Modulation technique used is Sinusoidal PWM. To give input DC voltage is 200 volts. DC link divides the given voltage to two equal quantities. The generated gate pulses from single PWM techniques give to respected IGBT. Observe the output wave form on analyser. Fig. 4.6 shows the output line voltage and current with a RL load of 78Ω, 36mH whose amplitude is around 98 volts which is close to 100 volts. 47

TABLE 4.2 SIMULATION PARAMETERS FOR SINUSOIDAL-PHASE INVERTER Parameters

Value

R int and R snubber of IGBT

0.01 Ω, 105 Ω

V dc

200 volts

Load

R = 78 Ω, L = 36 mH

Modulation Index M f carrier

0.85 1 kHz

f ref

50 Hz 2200µF, 200 mΩ

Capacitance and R ESR of dc-link

Fig. 4.6 Phase Voltage & Current waveforms of 3-level NPC-MLI with R L-load

(a)

(b)

(c)

(d)

Fig 4.7 Harmonic spectrum of a phase voltage (a)PD (b)POD (c)APOD (d)LS

48

The voltage THD Of a PD, POD, APOD & LS are 37.63%, 39.91%, 42.57% and 37.59% respectively. The harmonic spectrum of phase voltage with a different modulation techniques are show in Fig. 4.7. The %THD of a voltage is better with the PD, LS modulations techniques because of more modulation index. While using PD, LS modulation schemes less stress on switches. 4.2.2 3phase3-Level Inverter: The simulink model of a 3 level 3 phase NPC multilevel inverter is shown in the Fig. 4.8. The input voltage of 100 volts is separated by DC link. To give a gate pulse to the respective IGBTs having parameters are shown in Table 4.3 and the line voltage& line current waveforms and phase voltage & phase current with a simple R-L load of 78Ω, 36mh is shown in the Fig. 4.9 & 4.10 respectively.

Fig. 4.8 Simlink model of a NPC 3phase 3 level with RL load TABLE 4.3 SIMULATION PARAMETERS FOR SINUSOIDAL-PHASE INVERTER Parameters

Value

R int and R snubber of IGBT

0.01 Ω, 105 Ω

V dc

100 volts

Load

R = 78 Ω, L = 36 mH

Modulation Index M f carrier

0.85 1 kHz

f ref

50 Hz

Capacitance and R ESR of dc-link

2200µF, 200 mΩ

49

Fig. 4.9 Line voltage & line current of a 3 phase 3 level NPC- MLI

The line voltage and line currents are 50v & 2.3A. The voltage and current THD are shown in the Fig. 4.11& 4.12 respectively. The voltage THD is of a 3phase 3level NPC is 23.65% and current THD is 1.68%.

Fig. 4.10 Phase voltage & phase current of a 3 phase 3 level NPC- MLI

Using single pulse width modulation the harmonic spectrum of a 3 level is more than sinusoidal pulse width modulation because it is having better duty ratio

50

Fig. 4.11 Harmonic spectrum of Phase voltage

Fig. 4.12 Harmonic spectrum of Phase current

4.2.3 5-Level Inverter: The simulink model of a 5 level Neutral point clamped multilevel inverter is simulated. Values of various parameters used in this model are given in Table 4.4. Modulation technique used is Sinusoidal PWM. To give input DC voltage is 100 volts. DC link divides the given voltage to two equal quantities. The generated gate pulses from single PWM techniques give to respected IGBT. Observe the output wave form on analyser. Fig. 4.13 shows the output line voltage and current with a RL load of 78Ω, 36mH whose amplitude is around 98 volts which is close to 100 volts. The voltage THD of a PD, POD, and APOD & LS are 36.89%, 39.41%, 41.69% and35.81% respectively. The harmonic spectrum of phase voltage with a different modulation techniques are show in Fig. 4.14. The %THD of a voltage is better with the PD, LS modulations techniques because of more modulation index. While using PD, LS modulation schemes less stress on switches.

TABLE 4.4 SIMULATION PARAMETERS FOR SINUSOIDAL-PHASE INVERTER Parameters

Value

R int and R snubber of IGBT

0.01 Ω, 105 Ω

V dc

100 volts

Load

R = 78 Ω, L = 36 mH

Modulation Index M f carrier

0.85 1 kHz

f ref

50 Hz

Capacitance and R ESR of dc-link

2200µF, 200 mΩ

51

Fig. 4.13 Line voltage and line current of a 5 level NPC-MLI

(a)

(b)

(c) (d) Fig 4.14 Harmonic spectrum of a phase voltage (a)PD (b)POD (c)APOD (d)LS

4.2.4 3 phase 5-Level Inverter: The simulink model of a 3 level 5 phase NPC multilevel inverter is simulated. The input voltage of 400 volts is separated by DC link. To give a gate pulse to the respective IGBTs having parameters are shown in table 4.1 and the line voltage& line current waveforms and phase voltage & phase current with a simple R-L load of 78Ω,36mh is shown in the Fig.. 4.15 &4.16 respectively. The line voltage and line currents are 235v & 2.3A. The voltage and current THD are shown in the Fig. 4.17& 4.18 respectively. The voltage THD is of a 3phase 3level NPC is 38.65% and current THD is 1.37%. 52

Fig. 4.15 Phase voltage & phase current of a 3 phase 5 level NPC- MLI

Fig. 4.16 Line voltage & line current of a 3 phase 5 level NPC- MLI

The %THD of a 3 level is better than 5 level inverter because incensing number of levels there is problem with a dc link. While increasing the number of levels number of dc link capacitors also increased so that difficult to balancing the voltage level.

53

Fig. 4.17 Harmonic spectrum of Phase voltage

Fig. 4.18 Harmonic spectrum of Phase current

4.3 COMPARISON A Comparison made between 3 level and 5 level with a different modulation techniques as PD,POD,APOD & PS of a %THD of current and voltage as show in Table 4.5. TABLE 4.5 COMPARISON OF 3 & 5 LEVEL INVERTER WITH DIFFERENT MODULATION TECHNIQUES

3 LEVEL

5 LEVEL

PD

POD

APOD

PS

PD

POD

APOD

PS

Voltage

37.63

39.91

42.57

37.59

36.89

39.41

41.69

35.81

Current

12.25

13.82

17.12

14.89

11.23

13.56

16.14

11.34

5.3 SUMMARY This chapter shows the simulation results for both single-phase and three-phase NPC inverters with a Single pulse and sinusoidal pulse width modulation. Simulink models of both the cases are developed in MATLAB/SIMULINK environment. Waveforms for output voltage and current in both the cases are shown and analyzed. In comparison of 3 level and 5 level NPC MLI with a different modulation techniques. The phase disposition (PD) and phase shift (PS) having a better harmonic spectrum because of more modulation index. 3 level 3 phase inverter is a better for motor drives applications because of 5 level having a problem with a voltage balancing of dc link it is rectified by closed loop so that increasing the number of levels with the difficulty with the voltage balancing.

54

CHAPTER 5

HARDWARE IMPLIMENTATION & EXPERIMENTAL RESULTS

55

CHAPTER 5

HARDWARE IMPLIMENTATION & RESULTS

The Design of three-level inverter is divided into two parts. One is hardware design and other is software design. Hardware design includes component-rating selection and power circuit. Software design includes the Core algorithms for three-level Neutral point clamped (NPC) inverter operations. The block diagram of the proposed inverter scheme is shown Fig. 5.1. Here TMS320f28335 processor is used to generate the gate pulses. An ePWM module is used to generate the gate pulses and is driven through gate driver circuit to give the pulses to the switches.

DC Source

3- level NPC Inverter

Load

Gate Driver

TMS320f28335 Fig. 5.1 Block Diagram for Hard ware Implementation

5.1 ENHANCED PULSE WIDTH MODULATOR (EPWM MODULE) The enhanced pulse width modulator (ePWM) peripheral is a key element in controlling many of the power electronic systems found in both commercial and industrial equipments. These systems include digital motor control, switch mode power supply control, uninterruptible power supplies (UPS), and other forms of power conversion. An effective PWM peripheral must be able to generate complex pulse width waveforms with minimal U overhead or intervention. It needs to be highly programmable and very flexible while being easy to understand and use. The ePWM unit described here addresses these requirements by allocating all needed timing and control resources on a per PWM channel basis. The ePWM module represents one complete PWM channel composed of two PWM outputs: EPWMxA and EPWMxB. Multiple ePWM modules are instanced within a

56

device.The ePWM modules are chained together via a clock synchronization scheme that allows them to operate as a single system when required. Additionally, this synchronization scheme can be extended to capture peripheral modules (eCAP). The number of modules is device-dependent and based on target application needs. Modules can also operate standalone. Each ePWM module s the following features: 

Dedicated 16-bit time-base counter with period and frequency control



Two PWM outputs (EPWMxA and EPWMxB) that can be used in the following configurations  Two independent PWM outputs with single-edge operation  Two independent PWM outputs with dual-edge symmetric operation  One independent PWM output with dual-edge asymmetric operation



Asynchronous override control of PWM signals through software.



Programmable phase-control for lag or lead operation relative to other ePWM modules.

Fig. 5.2 multiple ePWM Modules

57



Hardware-locked (synchronized) phase relationship on a cycle-by-cycle basis.



Dead-band generation with independent rising and falling edge delay control.



Programmable trip zone allocation of both cycle-by-cycle trip and one-shot trip on fault



A trip condition can force either high, low, or high-impedance state logic levels at PWM Outputs



All events can trigger both U interrupts and ADC start of conversion (SOC)



Programmable event prescaling minimizes U overhead on interrupts.



PWM chopping by high-frequency carrier signal, useful for pulse transformer gate drives. In DSPf28335 there are 6 ePWM peripherals which are connected as shown in the

Fig.. 5.2. Seven sub modules are included in every ePWM peripheral. Each of these sub modules performs specific tasks that can be configured by software. The block diagram showing the sub modules of an ePWM module is shown in the Fig.. 5.3.

Fig. 5.3 Sub modules of an ePWM module

5.1.1 TIME-BASE (TB) MODULE Each ePWM module has its own time-base submodule that determines all of the event timing for the ePWM module. Built-in synchronization logic allows the time-base of multiple ePWM modules to work together as a single system. 5.2.1.1 Purpose of the Time-Base (TB) Sub module We can configure the time-base sub module for the following:

58



Specify the ePWM time-base counter (TBCTR) frequency.



Manage time-base synchronization with other ePWM modules.



Maintain a phase relationship with other ePWM modules.



Generate the following events:  CTR = PRD: Time-base counter equal to the specified period (TBCTR = TBPRD).  CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000).



Configure the rate of the time-base clock; a prescaled version of the U system clock (SYSCLKOUT). This allows the time-base counter to increment/decrement at a slower rate.

5.2.1.2 Controlling and monitoring the Time-base Sub module The block diagram in Fig.. 5.4 shows the critical signals and s of the time-base sub module. Table 5.1 provides descriptions of the key signals associated with the time-base sub module. TABLE 5.1 TIME-BASE SUB MODULE S



Address offset

Shadowed

Description

TBCTL

0x0000

No

Time-Base Control

TBSTS

0x0001

No

Time-Base Status

TBPHSHR

0x0002

No

HRPWM Extension Phase

TBPHS

0x0003

No

Time-Base Phase

TBCTR

0x0004

No

Time-Base Counter

TBPRD

0x0005

Yes

Time-Base Period

Fig. 5.4 Time-Base Sub module Signals and s

59

5.1.2 COUNTER-COMPARE (CC) SUB MODULE The counter-compare sub module takes as input the time-base counter value. This value is continuously compared to the counter-compare A (CMPA) and counter-compare B (CMPB) s. When the time-base counter is equal to one of the compare s, the counter-compare unit generates an appropriate event. 5.1.2.1 Purpose of the Counter-Compare Sub module The counter-compare: 

Generates events based on programmable time stamps using the CMPA and CMPB s  CTR = CMPA: Time-base counter equals counter-compare A (TBCTR = CMPA).  CTR = CMPB: Time-base counter equals counter-compare B (TBCTR = CMPB)



Controls the PWM duty cycle if the action-qualifier sub module is configured appropriately



Shadows compare values to prevent corruption or glitches during the active PWM cycle

5.1.2.2 Controlling and monitoring the Counter-Compare Sub module The counter-compare sub module operation is controlled and monitored by the s shown in Table 5.2. The detailed view of the Counter-Compare Sub module is shown in the Fig. 5.5.

Fig. 5.5 Detailed view of the Counter-Compare Sub module.

60

TABLE 5.2 COUNTER-COMPARE SUB MODULE S

Name

Address Offset

Shadowed

Description

CMPCTL

0x0007

No

Counter-Compare Control .

CMPAHR

0x0008

Yes

HRPWM CC A Extension

CMPA

0x0009

Yes

Counter-Compare A .

CMPB

0x000A

Yes

Counter-Compare B .

5.1.3 ACTION-QUALIFIER (AQ) SUB MODULE The action-qualifier sub module is responsible for the following: 

Qualifying and generating actions (set, clear, toggle) based on the following events:  CTR = PRD: Time-base counter equal to the period (TBCTR = TBPRD).  CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)  CTR = CMPA: Time-base counter equal to the counter-compare A (TBCTR = CMPA)  CTR = CMPB: Time-base counter equal to the counter-compare B (TBCTR = CMPB)



Managing priority when these events occur concurrently



Providing independent control of events when the time-base counter is increasing and when it is decreasing.

5.1.3.1 Action-Qualifier Sub module Control and Status Definitions The action-qualifier submodule operation is controlled& monitored by the s in Table 5.3. TABLE 5.3 ACTION-QUALIFIER (AQ) SUB MODULE S



Address offset

Shadowed

Description

AQCTLA

0x000B

No

Action-Qualifier Control For Output A

AQCTLB

0x000C

No

Action-Qualifier Control For Output B

AQSFRC

0x000D

No

Action-Qualifier Software Force

AQCSFRC

0x000E

Yes

Action-Qualifier Continuous Software Force

The action-qualifier submodule controls how the two outputs EPWMxA and EPWMxB behave when a particular event occurs. The event inputs to the action-qualifier submodule are further qualified by the counter direction (up or down). This allows for independent action on outputs on both the count-up and count-down phases. Actions are

61

specified independently for either output (EPWMxA or EPWMxB). Any or all events can be configured to generate actions on a given output. For example, both CTR = CMPA and CTR = CMPB can operate on output EPWMxA. For clarity, the drawings in this document use a set of symbolic actions. These symbols are summarized in Fig. 5. Each symbol represents an action as a marker in time. Some actions are fixed in time (zero and period) while the CMPA and CMPB actions are moveable and their time positions are programmed via the countercompare A and B s, respectively. To turn off or disable an action, use "Do Nothing option"; it is the default at reset. The possible Action-Qualifier Actions for EPWMxA and EPWMxB are shown in the Fig. 5.6.

Fig. 5.6 Possible Action-Qualifier Actions for EPWMxA and EPWMxB Outputs

5.1.4 DEAD-BAND GENERATOR (DB) SUBMODULE The "Action-qualifier (AQ) Module" section discussed how it is possible to generate the required Dead-band by having full control over edge placement using both the CMPA and CMPB resources of the ePWM module. However, if the more classical edge delay-based dead-band with polarity control is required, then the dead-band sub module described here should be used. The key functions of the dead-band module are: Generating appropriate signal pairs (EPWMxA and EPWMxB) with dead-band relationship from a single EPWMxA input 

Programming signal pairs for:  Active high (AH)  Active low (AL)

62

 Active high complementary (AHC)  Active low complementary (ALC) 

Adding programmable delay to rising edges (RED)



Adding programmable delay to falling edges (FED)



Can be totally byed from the signal path (note dotted lines in diagram)

5.1.4.1 Controlling and Monitoring the Dead-Band Submodule The dead-band submodule operation is controlled and monitored by the s shown in Table 5.4. And the configuration options had shown in the Fig 5.7. TABLE 5.4 DEAD-BAND GENERATOR SUBMODULE S



Address offset

Shadowed

Description

DBCTL

0x000F

No

Dead-Band Control

DBRED

0x0010

No

Dead-Band Rising Edge Delay Count

DBFED

0x0011

No

Dead-Band Falling Edge Delay Count

Fig. 5.7 Configuration Options for the Dead-Band Sub module

5.1.5 PWM-CHOPPER (PC) SUBMODULE The key functions of the PWM-chopper sub module are: 

Programmable chopping (carrier) frequency



Programmable pulse width of first pulse



Programmable duty cycle of second and subsequent pulses



Can be fully byed if not required

5.1.5.1 Controlling the PWM-Chopper Sub module The PWM-chopper submodule operation is controlled via the s in Table 5.5. 63

TABLE 5.5 PWM-CHOPPER SUBMODULE S

mnemonic

Address offset

Shadowed

Description

PCCTL

0x001E

No

PWM-chopper Control

5.1.6 TRIP-ZONE (TZ) SUBMODULE The key functions of the Trip-Zone submodule are: 

Trip inputs TZ1 to TZ6 can be flexibly mapped to any ePWM module.



Upon a fault condition, outputs EPWMxA and EPWMxB can be forced to one of the following: –

High, Low, High-impedance, No action taken



for one-shot trip (OSHT) for major short circuits or over-current conditions.



for cycle-by-cycle tripping (CBC) for current limiting operation.



Each trip-zone input pin can be allocated to either one-shot or cycle-by-cycle operation.



The trip-zone submodule can be fully byed if it is not required.

5.1.6.1 Controlling and Monitoring the Trip-Zone Submodule The trip-zone submodule operation is controlled and monitored through the following s: TABLE 5.6 TRIP-ZONE SUBMODULE S



Address offset

Shadowed

Description

TZSEL

0x0012

No

Trip-Zone Select

Reserved

0x0013

--

---

TZCTL

0x0014

No

Trip-Zone Control

TZEINT

0x0015

No

Trip-Zone Enable Interrupt

TZFLG

0x0016

No

Trip-Zone Flag

TZCLR

0x0017

No

Trip-Zone Clear

TZFRC

0x0018

No

Trip-Zone Force

5.1.7 EVENT-TRIGGER (ET) SUBMODULE The key functions of the event-trigger submodule are: 

Receives event inputs generated by the time-base and counter-compare submodules



Uses prescaling logic to issue interrupt requests and ADC start of conversion at:  Every event  Every second event

64

 Every third event 

Provides full visibility of event generation via event counters and flags



Allows software forcing of Interrupts and ADC start of conversion

5.1.7.1 Controlling and Monitoring the Event-Trigger Submodule The key s used to configure the event-trigger submodule are shown in Table 5.7. TABLE 5.7 EVENT-TRIGGER SUBMODULE S

Name

Address offset

Shadowed

Description

ETSEL

0x0019

No

Event-trigger Selection

ETPS

0x001A

No

Event-trigger Prescale

ETFLG

0x001B

No

Event-trigger Flag

ETCLR

0x001C

No

Event-trigger Clear

ETFRC

0x001D

No

Event-trigger Force

5.2 SOFTWARE IMPLEMENTATION Software algorithm is the heart of three-level inverter control algorithm. The Software algorithm is depicted in the flowchart as shown in Fig.. 5.8. 5.2.1 Procedure for the PWM Pulse Generation 1. Write the Program to generate the pulses. 2. Connect the DSPf28335 Board to the PC through RS232 cable. 3. Open the set up of code composer studio and select the target board configuration. 4. Open new Project in CCS. 5. Load the Main Program and the other ed files in to the CCS. 6. Build the Project. 7. Load the .out file into the DSP. 8. Run the Program. 9. Check the required pulses at the PWM port of the DSP. 10. Give the Pulses to the Gate Driver circuit of the Neutral Point Clamped. 11. The Required 3-level output is generated at the output terminals of the inverter. 12. Check the output 3 level wave form across output terminals.

65

START

Declaration and Initialization of system variables

Select the CMPA& CMPB values

Generate the triangular wave using Timer

Compare the Instantaneous value of CMPA& CMPB with triangular wave to generate gate pulses

Give the sufficient dead band to the PWM signals

END

Fig. 5.8 Flow chart for software implementation

5.3 HARDWARE IMPLEMENTATION For the Power circuit, 4 IGBTs of Infineon make IKW40T120 has been used as a power switches. The main heart of the control signal board is DSP ‗TMS320F28335‘. This DSP has been used to control the various operations of three-level inverter. A programme is written with DSP kit to generate the PWM Signals, which is transferred to the GATE driver through FRC connector for the firing of the IGBT. The programming for the DSP ‗TMS320F28335‘ is done in the Code Composer Studio. The program is written in the ‗C‘ language is shown in Appendix. The program is transferred from PC to DSP ‗TMS320F28335‘ through a ‗JTAG emulator‘. The hardware setup is shown in Fig. 5.9

Fig. 5.9 Hardware setup of NPC-MLI 66

5.4 EXPERIMENTAL RESULTS For the experimental results follow the procedure above procedure discussed in chapter 5.2 and 5.2 and connect the load as R & RL and analyze the output by using power analyser. 5.4.1 R-LOAD (R= 94 Ω) To give 10 volts dc voltage form dc source, capacitor link separate the dc voltage. By using DSP the generated gate pulse to required switches will get an rms ac output voltage as 5v by using the parameters as show in Table 5.8. TABLE 5.8 PARAMETERS OF THE HARDWARE MODEL FOR R-LOAD Parameters

Value

R int and R snubber of IGBT

0.01 Ω, 105 Ω

V dc

10 volts

Load

R = 94 Ω

Modulation Index M f carrier

0.85 1 kHz

f ref

50 Hz

Capacitance and R ESR of dc-link

2200µF, 200 mΩ

The Phase voltage & current waveforms of a NPC 3-level inverter with resistive load of R= 76 ohm is shown in the Fig. 5.10 are 5.36 volts, 68.5mA respectively. The harmonic spectrums of phase voltage& phase currents are shown in the Fig.5.11 (a) & (b) respectively. The % THD of a voltage is 26.5% and %THD of a current is 26% which is nearly equal to simulation results as shown in Fig 4.2 discussed in chapter 4. The %THD is better for NPC – MLI while connect the motor this is no harm to the circuit.

Fig. 5.10 phase voltage & current wave forms of a NPC 3-level inverter with R-load

67

(a)

(b)

Fig. 5.11 Harmonic spectrum of (a) Phase voltage (b) phase current

5.4.2 R-L LOAD (R= 61 Ω, L=0.1 mH) To give 10 volts dc voltage form dc source, capacitor link separate the dc voltage. By using DSP the generated gate pulse to required switches will get a rms ac output voltage as 5v by using the parameters as show in Table 5.9. TABLE 5.9 PARAMETERS OF THE HARDWARE MODEL FOR RL LOAD Parameters

Value

R int and R snubber of IGBT

0.01 Ω, 105 Ω

V dc

10 volts

Load

R = 61 Ω,L=0.01

Modulation Index M f carrier

0.85 1 kHz

f ref

50 Hz

Capacitance and R ESR of dc-link

2200µF, 200 mΩ

The Phase voltage& current waveforms of a NPC 3-level inverter with R-L load of R= 61 Ω, L= 0.1 mH is shown in the Fig. 5.12. Form this wave forms the phase voltage is 5.31v and current is 147mA. Here small inductance value is taken because of that theirs is no phase difference between current and voltage the power factor is 0.93.And harmonic spectrums of phase voltage& phase currents are shown in the Fig.. 5.13(a) & (b) respectively. The values of voltage & current harmonic spectrum are 26.5% and 26.1% respectively.

Fig. 5.12 phase voltage & current wave forms of a NPC 3-level inverter with R-load 68

(a) (b) Fig. 5.13 Harmonic spectrum of (a) Phase voltage (b) phase current

R= 30 Ω, L=76.835 mH To give 10 volts dc voltage form dc source, capacitor link separate the dc voltage. By using DSP the generated gate pulse to required switches will get a rms ac output voltage as 5.24v by using the parameters as show in Table 5.10 TABLE 5.10 PARAMETERS OF THE HARDWARE MODEL FOR RL LOAD Parameters

Value

R int and R snubber of IGBT

0.01 Ω, 105 Ω

V dc

10 volts

Load

R = 30 Ω,L=76.85mH

Modulation Index M f carrier

0.85 1 kHz

f ref

50 Hz

Capacitance and R ESR of dc-link

2200µF, 200 mΩ

The Phase voltage& current waveforms of a NPC 3-level inverter with R-L load of R= 30 Ω, L= 76.85 mH is shown in the Fig. 5.14. Form this wave forms the phase voltage is 5.31v and current is 147mA. Because of inductance value form the Fig 5.14 clearly observes that the phase displacement between current and voltage and the power factor is 0.77. The harmonic spectrums of phase voltage& phase currents are shown in the Fig. 5.15(a) & (b) respectively. The values of voltage & current harmonic spectrum are 27.9% and 10.7% respectively. Clearly observe form the %THD of current is less than to connect the R load. It is nearly equal to the simulation results as show in Fig 4.3 discussed in chapter 4.

69

Fig. 5.14 phase voltage & current wave forms of a NPC 3-level inverter with R-load

(a)

(b)

Fig. 5.15 Harmonic spectrum of (a) Phase voltage (b) phase current

5.5 SUMMARY This chapter analyze the experimental results of a 3 level neutral point clamped multi level inverter with an R and RL load. While observing the experimental results the voltage and current waveforms having less number of even harmonics and better harmonic spectrum. When connected the R L load the phase different between voltage and current also observed and the harmonics spectrum of the current is decreased so that to connect a induction motor which is also a R L Load

70

CHAPTER 6 CONCLUSION & FEATURE SCOPE

71

CHAPTER 6

CONCLUSION & FEATURE SCOPE

6.1 CONCLUSION

The multilevel inverter topology can overcome some of the limitations of the Standard two-level inverter. Output voltage and power increase with number of levels. Harmonics decrease as the number of levels increase. In addition, increasing output voltage does not require an increase in voltage rating of individual devices. In the thesis, several multilevel voltage source inverters and their modulation topologies are introduced and the Neutral point clamped multilevel inverter for drives applications. This work presents the different modulation techniques i,e PD,POD,APOD,PS. For NPC-MLI used different modulation techniques among these modulation techniques PD, LS has a better %THD because of more duty ratio. The NPC-MLI for 3-level with single pulse modulation and 3 phase 3-level & 3 phase 5 level with SPWM also simulated and the voltage& current harmonic spectrum is compared for R-L load. The hardware is implemented for single pulse modulated NPC-MLI inverter using DSPf28335. DSP& FPGA processors are the effective solution for controlling the gate signals of the multilevel inverters. The THD of voltage& current for R& R-L loads are observed. This 3 level inverter has the better harmonic profile comparing with a conventional two level inverter. From the simulation and experimental results NPC-MLI has a better harmonic spectrum than other MLI topologies. 3 phase-3 level NPC- MLI is easy to implement and this topologies can be applicable for the Drives application& Renewable energy applications.

72

6.2 FEATURE SCOPE Multilevel power conversion technology is a very rapidly growing area of power electronics with good potential for further development. Today, it is hard to connect a single power semiconductor switch directly to medium voltage grids. For these reasons, a new family of multilevel inverters has emerged as the solution for working with higher voltage levels. Multilevel inverters are increasingly being used in high-power medium voltage applications due to their superior performance compared to two-level inverters. 1. From the simulation study it is observed that the harmonics in the current is further reduced in the sinusoidal pulse width modulation in comparison with single pulse modulation. Some application needs the other topologies and modulation schemes of MLIs which are also can be easily implemented using DSP processors for future aspect. 2. In the diode clamped multilevel inverter there is a problem of voltage balancing because of the presence of capacitors, for which we can implement a closed loop control 3. Voltage THD is less with single pulse width modulation over SPWM, but the current Harmonic spectrum is better with SPWM. And the current wave form is also almost sinusoidal in SPWM which is essential requirement for the Induction motor drives 4. NPC there are some more control techniques such as SVPWM, SHE-PWM for some applications. All these things can be implemented on DSP& FPGA processors with simple programming techniques for the future study 5. In many industrial applications, the supply currents are not purely sinusoidal in nature but are distorted. Supply power quality can be improved by using multiple converters as front-end converter with MLI. However, a lot needs to be done in the area of modelling & operation of the multilevel inverter. 6. Practical implementation of multilevel inverters for high power applications is still an issue as a higher level inverters a large no of devices and hence large size & cost. It also involves complexity in control. Lot of research needs to be done on developing new multilevel inverter topologies which behave as higher level inverters but with reduced number of switches.

73

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APPENDEX ********************************************************************** * File: NPC.c * Devices: TMS320F2833x ********************************************************************** #include "DSP28x_Project.h"

// Device Headerfile and Examples Include File

#define EPWM1_MAX_DB 0x03FF // Maximum Dead Band values #define EPWM2_MAX_DB 0x03FF #define EPWM1_MIN_DB 0x03FE #define EPWM2_MIN_DB 0x03FE void main(void) { // Step 1. Initialize System Control: InitSysCtrl(); // Step 2. Initalize GPIO: InitEPwm1Gpio(); InitEPwm2Gpio(); // Step 3. Clear all interrupts and initialize PIE vector table: DINT; InitPieCtrl(); InitPieVectTable(); // Step 4. Initialize all the Device Peripherals: InitEPwm1Example(); InitEPwm2Example(); void InitEPwm1Example() { EPwm1Regs.TBPRD = 46875;

// Set timer period

EPwm1Regs.TBPHS.half.TBPHS = 0x0000; EPwm1Regs.TBCTR = 0x0000;

// Phase is 0 // Clear counter

// Setup TBCLK EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up

79

EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;

// Disable phase loading

EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV8; EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV4;

// Clock ratio to SYSCLKOUT // Slow just to observe on the scope

// Setup compare EPwm1Regs.CMPA.half.CMPA = 4687; EPwm1Regs.CMPB = 42188; // Set actions EPwm1Regs.AQCTLA.bit.CBU = AQ_SET; EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;

// Set PWM1A on Zero

EPwm1Regs.AQCTLB.bit.CBU = AQ_SET;

// Set PWM1B on Zero

EPwm1Regs.AQCTLB.bit.CBD = AQ_CLEAR; // Active Low complementary PWMs - setup the deadband EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_LOC; EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL; EPwm1Regs.DBRED = EPWM1_MIN_DB; EPwm1Regs.DBFED = EPWM1_MIN_DB; EPwm1_DB_Direction = DB_UP; EPwm1Regs.DBFED = 100; EPwm1Regs.DBRED = 100; // Interrupt where we will modify the deadband EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; EPwm1Regs.ETSEL.bit.INTEN = 1;

// Select INT on Zero event

// Enable INT

EPwm1Regs.ETPS.bit.INTPRD = ET_3RD;

// Generate INT on 3rd event

} void InitEPwm2Example() { EPwm2Regs.TBPRD = 46875;

// Set timer period

EPwm2Regs.TBPHS.half.TBPHS = 0x0000; EPwm2Regs.TBCTR = 0x0000;

// Phase is 0 // Clear counter

// Setup TBCLK 80

EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;

// Disable phase loading

EPwm1Regs.TBCTL.bit.SYNCOSEL =TB_SYNC_IN; EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV8; EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV4;

// Clock ratio to SYSCLKOUT // Slow just to observe on the scope

// Setup compare EPwm2Regs.CMPA.half.CMPA = 4687; EPwm2Regs.CMPB = 42188; // Set actions EPwm2Regs.AQCTLA.bit.CAU = AQ_SET;

// Set PWM2A on Zero

EPwm2Regs.AQCTLA.bit.CBD = AQ_CLEAR; EPwm2Regs.AQCTLB.bit.CBU = AQ_CLEAR;

// Set PWM2A on Zero

EPwm2Regs.AQCTLB.bit.CBD = AQ_SET; // Active Low complementary PWMs - setup the deadband EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL; EPwm2Regs.DBRED = EPWM2_MIN_DB; EPwm2Regs.DBFED = EPWM2_MIN_DB; EPwm2_DB_Direction = DB_UP; EPwm2Regs.DBFED = 100; EPwm2Regs.DBRED = 100; // Interrupt where we will modify the deadband EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; EPwm2Regs.ETSEL.bit.INTEN = 1;

// Select INT on Zero event

// Enable INT

EPwm2Regs.ETPS.bit.INTPRD = ET_3RD;

// Generate INT on 3rd event

}

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