Design Of A Discrete Bjt Operational Amplifier 4m6r43
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EE323: DESIGN OF A BJT OP-AMP
1
Design of a Discrete BJT Operational Amplifier Michael Jones, Student Member, IEEE, Audio Engineering Society
Abstract—The operational amplifier consists three basic stages. • High Impedance, Differential Input Amplifier • Voltage Amplification Stage • Single-Ended Low Impedance Output The components, and stages of an integrated circuit op-amp are direct-coupled. Direct coupling presents many challenges to the designer. These challenges will be explored, as a simple, three stage discrete BJT op-tamp will be designed, simulated, characterized, and finally implemented.
Many of the design restrictions, and challenges in analog IC design arise from limited chip size. Therefore, resistances are kept low, and the use of capacitors is limited. Other active devices, such as inductors, are impractical due to their size. Transistors, due to their small size, are called upon to provide many functions in the integrated circuit; including resistance (active-loads), current/voltage amplification, and the creation of current sources, i.e.current mirrors, for biasing. Transistors are the most numerous component in any IC. Another challenge in IC design comes from the direct coupling of transistors. Transistors must be biased so that they provide their intended functionality, while properly biasing transistors they are directly coupled to. This biasing point of a transistor is also called the quiescent operating point, Q-point, or DC operating point. A BJT transistor can be biased with a current, or a voltage. Proper biasing is one of the most important steps in the design of integrated circuits. An IC op-amp is a directcoupled high-gain amplifier, usually consisting of one or more differential amplifiers, followed by a DC level shifter, and a low impedance output stage [1]. The following paper presents the design, analysis, and implementation of a discrete BJT operational amplifier, using direct coupling, and no capacitors. II. C IRCUIT T OPOLOGY A. Differential Input Stage The first stage of the op-amp is a differential amplifier with high input impedance, see figure 1. A Darlington Pair at the input increases the input impedance by a factor of β. The input impedance of the op-amp is equal to the input impedance of the first stage. It is calculated with equation 1 (1)
A cascode current mirror was designed to sink 1mA. This current biases the first stage. The 1mA current gets divided equally between transistor pairs, Q1,2 , and Q3,4 , see Appendix A. The cascode current mirror was chosen for it’s large output impedance, ro! , see equations 2, 3. This impedance reduces the common mode gain, eq. 5, and increases the common mode rejection ration, (CMRR), eq. 6.
|VA | Ibias
ro!cascode = β(ro! ) Avdb = Acm =
I. I NTRODUCTION
Zin = 2βQ1 βQ2 (re!2 + RE1)
ro! =
re!
−Rc re! + Re
−Rc + Re + 2ro!cascode
(2) (3) (4) (5)
Avdb re! + Re + 2ro!cascode = (6) Acm re! + Re Emitter degeneration, RE1, and RE2, was used as a form of negative for this stage. The addition of these resistors reduces the gain of the stage, eq. 4, and increases the input impedance, eq. 1. However, emitter degeneration helps to reduce non-linear distortion, and increase the large-signal transfer characteristic [2], [3]. The value for RE1, and RE2 was determined using equation 7, [2]. CM RR =
Re =
40VT Ibias
(7)
A comparison of figures 2, and 3 demonstrates the effect emitter degeneration has on the linear operating range. RC1 and RC2 are used to drop a third of the supply voltage at the nodes Vout1, and Vout2. These collector resistors also affect the final gain of the stage, eq. 4. Table I lists these parameter values. The experimental output of the first stage circuit can be viewed in figure 4. B. Voltage Amplification Stage This stage is designed for large amounts of gain. An active load is used to achieve a large resistance value, eq. 2. The PNP transistors used have an early voltage, VA , equal to 120V. The transistors are being biased with 2mA; therefore, the active load is equivalent to 60kΩ. Active loads make large gains possible, without taking up too much ”real estate”. The gain of the second stage can be calculated with eq.8. A cascode current mirror was chosen to bias transistors Q9 , Q10 , Q11 , and Q12 . However, unlike the first stage, eq.9 is used to calculate the CMRR. ro! + Re)
(8)
Avds re! + Re + 2ro!cascode = Acm 2(re! + Re)
(9)
Avds = CM RR =
2(re!
VOU T 3 = (IcQ12 − IcQ10 )ro!Q12
(10)
EE323: DESIGN OF A BJT OP-AMP
2
Emitter degeneration was used again to increase linearity, and reduce distortion [2]. The biasing of the output, Vout3, of this stage is not as straight forward as the biasing of the first stage’s output. The impedance the amplifier sees looking into the collector of Q12 is not the same impedance the current sees looking into the emitter of that transistor. This voltage drop can be estimated by using equation 10, [5]. This equation still gives you a ”ballpark” figure. It is also worthwhile to note that this voltage drop is current dependent. One has to keep in mind that an increase in current causes a decrease in ro’. The fine tuning of R2 allows one to see the effect that the bias current has on the operating point of V out3. Figures 5, and 6 show the experimental, and SPICE output waveforms for this stage. Both figures display output distortion.This distortion is due to the lack of headroom at Vout3. The voltage amplification stage provides a gain of ≈ 60. See table I. C. DC Level Shifter and Class A-Output Stage The last two stages of the op-amp are composed of a P N P common emitter (CE) amplifier, and a N P N emitter follower, [2]. The P N P acts as a DC level shifter, and as the last gain stage for the op-amp, eq.11, ACE =
−Rc3 re! + Re5
(11)
The +0.7V shift from V out3 to the emitter of Q17 allows the the P N P to be biased with a current of the designer’s choosing. This current, IQ17 will be: IQ17 =
V pp−VE17 RE5
A current of ≈ 1.1mA was chosen. The additional 100uA s for the base current of transistor Q18 . This base current was calculated as follows. Ibase =
Ibias βQ18
The voltage at node VC17 is selected to be ≈ +0.7V above the desired output value. Node VC17 was biased at 1V . The resistor RC3 accomplishes this biasing, and it’s value is calculated as follows: RC17 =
1V −VN N IRC3
Note: RE5 , and RC3 must be carefully selected, as each affects the biasing of Q17 , and the output voltage offset. The emitter follower, Q13 , is biased with a cascode current mirror that sinks 11.3mA of current. The emitter resistance for the N P N emitter follower is ro!Q20 . This stage is a class A output stage. An amplifier in which the transistor is on for the entire output cycle is called ”class A” [3]. This output was chosen for it’s simplicity, and it’s linearity [3]. The output node V out has a final theoretical offset of 0.3V , see Appendix A. Figure 7, and 8 shows the SPICE, and experimental output of the discrete BJT operational amplifier. It is not possible to attain an input voltage in the laboratory that is low enough to obtain an accurate open loop gain of the operation amplifier. Hence, the voltage output in fig.8 is ”railing”. The linearity of the operational amplifier can be seen in figure 9, which shows the offset of the output, at +358mV input. Figure 9 also shows
that the op-amp will behave linearly for a voltage input of -2mV to 1mV. III. C HARACTERIZATION Table II shows various characterization parameters for the simulated circuit. The input bias current can be found by measuring the base currents of transistors, Q1 , andQ3 [1]. The input offset current can be found by calculating the folllowing: Iof f set = |IBQ1 − IBQ2 |
The input offset voltage is defined as the voltage that must be applied at the input to null the output [1]. This value was found by grounding the inverting input, and sweeping the DC source of the non-inverting. The frequency response of the simulated circuit is shown in figure 10. Figure 10 was used to find the value for ft , and fBOL . It is worth noting that the fBOL for a µ741A is around 10Hz. The low fBOL for a µ741A is due to the presence of a small, ≈ 30pF , frequency compensating capacitor in the circuit [4]. The slew rate of the op-amp was tested with the circuit in figure 13. This circuit tests how fast the op-amp can track the input voltage. The slew rate is defined in equation 12. Similar to the fBOL , the slew rate is higher for an amplifier without a capacitor. Equation 13 shows the relationship between slew rate and capacitance. Capacitance reduces slew rate [4]. The value obtained during the SPICE simulation is highly dependent on the accuracy of the model for the transistors used. The accuracy of the value obtained is questionable, see table II. SR =
dVout |maximum dt
dVout I = dt C
(12)
(13)
It is interesting to view the common mode output as a function of frequency, figure 14. The CMRR of this op-amp degrades after 10kHz, at an average rate of about −20dB dec . IV. N EGATIVE F EEDBACK C IRCUITS The op-amp was placed in Inverting, and Non-Inverting circuit configurations to test it’s operation in negative , figure 15. Figure 10 displays the effect closed loop gain has on the frequency response of the op-amp. Notice, as ACL , decreases,fBCL increases. This relationship is well defined, and is termed the Gain − Bandwidth P roduct, see equation 14. ft = AOL fBOL = ACL fBCL
(14)
Figure 16 shows the simulated output of the op-amp when placed in non-inverting configuration. The design behaves, as expected. Figure 11 shows the experimental output when the circuit is configured as a non-inverting voltage follower. Table III displays the gain calculated from figure 11.
EE323: DESIGN OF A BJT OP-AMP
3
V. E XPERIMENTAL R ESULTS The op-amp circuit designed was built, and tested stage, by stage in the laboratory. The first stage performed well. The bias voltage, and currents were comparable to theoretical, and SPICE values. However, the first stage of gain was less than expected. The second stage performed as expected. Figures 5, and 6 display the similarity between simulated, and experimental results. Table I shows the gain of the second stage varies from both SPICE, and theoretical. However, the cumulative gain Avd1 × Avd2
is 505 for SPICE, and 497, for experimental. These results are very close. The last stage did show clipping, in response to the smallest input that could be obtained in the laboratory, ≈ 10mV , see figure 8. This result was expected. The experimental circuit behaved erratically when placed in negative . The circuit would work as a voltage follower; however, fine tuning of resistors RE5 , and RC5 , along with checking, and re-checking the bias points, and currents of the P N P CommonEmitter stage was required. It was not possible to obtain results for closed loop gains higher than one. These difficulties made further experimental characterization of the device nearly impossible. During troubleshooting, It was found that DC bias point of node VC17 was higher than expected. It was also found that the output of the BJT op-amp was biased at -2.8V. Standard troubleshooting measures were taken; including, checking wiring, breadboard functionality, and signal chain continuity. Additional emitter resistance was added to Q18 , in an attempt raise the DC offset at output. This resistance was shown to raise output voltage offset in SPICE; however, it did not change the offset value in the laboratory.
Fig. 1.
Discrete BJT Operational Amplifier Circuit Topology
Fig. 2.
Transfer Characteristic of First Stage without Emitter Degeneration
Fig. 3.
Transfer Characteristic of First Stage with Emitter Degeneration
VI. D ISCUSSION AND C ONCLUSION The obvious flaw in the design of this discrete operational amplifier lies in the output stage. The implementation of a CE/CC output stage is difficult. Inherent difficulties lie in choosing values for RC3, and RE5 that will create the proper bias current for the P N P , and provide the proper level shift for the desired output voltage. This type of output stage does not provide any temperature compensation. Voltage offset at the output will drift with temperature changes. Further investigation into output stage, topology and negative is required to obtain a stable operational amplifier.
TABLE I D EVICE PARAMETERS FOR BJT O PERATIONAL A MPLIFIER Device Paramaters Zin Zout Avd1 Avd2 Avd3 Total Avd Acm1 Acm2 AcmTotal CMRR
SPICE 9.50M Ω 230Ω 6.4 79 12.2 6723 -61dB -38db -77dB 153.5dB
Theoretical 21M Ω 136Ω 9.6 63.4 12.8 6513 -66dB -44dB -110dB 186dB
Experimental 20.8M Ω x 4.36 114 x 870 -14dB x x 73dB
EE323: DESIGN OF A BJT OP-AMP
Fig. 4.
Fig. 5.
Fig. 6.
4
Fig. 7.
SPICE Simulated Maximum OutputSwing of Operational Amplifier
Fig. 8.
Experimental Maximum OutputSwing of Operational Amplifier
Fig. 9.
SPICE Generated Voltage Transfer Characteristic of BJT Op-Amp
Output of Differential Input Stage
Gain and DC Offset of Voltage Amplification Stage
SPICE Simulated Output of Voltage Amplification Stage Fig. 10.
Frequency Response of BJT Operational Amplifier
EE323: DESIGN OF A BJT OP-AMP
5
A PPENDIX A DC B IAS P OINT A NALYSIS
Fig. 11.
BJT Op-Amp Configured as Non-Inverting Voltage Follower
Fig. 12.
Test Circuit used to Determine SlewRate
Fig. 13.
Output of Voltage Follower used to Determine Slew Rate
Fig. 14.
Frequency Response of Common Mode Output
Bias Point Vout1 Vout2 Vout3 Vout J1 J2 VE17 VC17 Vm1 Vm2 Vm3 Vm4 Ic(Q1): Ib(Q1): Ie(Q1): Ic(Q2): Ib(Q2): Ie(Q2): Ic(Q3): Ib(Q3): Ie(Q3): Ic(Q4): Ib(Q4): Ie(Q4): I(Rc1): I(Rc2): I(R1): Ic(Q5): Ib(Q5): Ie(Q5): Ic(Q6): Ib(Q6): Ie(Q6): Ic(Q7): Ib(Q7): Ie(Q7): Ic(Q8): Ib(Q8): Ie(Q8): Ic(Q9): Ib(Q9): Ie(Q9): Ic(Q10): Ib(Q10): Ie(Q10):
SPICE 9.98 9.97 12.84 0.36 -1.63 8.34 13.50 1.55 -13.69 14.33 -13.61 -13.52 4.64E-06 1.04E-07 -4.7E-06 4.8E-04 4.7E-06 -4.8E-04 4.6E-06 1.0E-07 -4.7E-06 4.8E-04 4.7E-06 -4.8E-04 5.0E-04 5.0E-04 1.0E-03 9.9E-04 1.0E-05 -1.0E-03 9.7E-04 1.1E-05 -9.8E-04 9.8E-04 9.9E-06 -9.9E-04 9.8E-04 9.9E-06 -9.9E-04 1.9E-03 1.8E-05 -1.9E-03 1.9E-03 2.4E-05 -1.9E-03
Theoretical 10.00 10.00 13.00 0.30 -1.40 9.30 13.70 1 -13.60 14.30 -13.60 -13.60 5.50E-04 5.00E-08 -5.0E-06 5.0E-04 5.0E-06 -5.0E-06 5.0E-04 5.0E-08 -5.0E-06 5.0E-04 5.0E-06 -5.0E-06 5.0E-04 5.0E-04 1.0E-03 1.0E-03 1.0E-05 -1.0E-03 1.0E-03 1.0E-05 -1.0E-03 1.0E-03 1.0E-05 -1.0E-03 1.0E-03 1.0E-06 -1.0E-03 2.0E-03 2.0E-05 -2.0E-03 2.0E-03 2.0E-05 -2.0E-03
Experimental 9.9 9.9 12.6 -2.8 -1.54 8.3 13.2 5.3 -13.6 14.3 -13.6 -13.6 x x x x x x x x x x x x x x x x x x 9.80E-04 x x x x x x x x x x x x x x
Units V V V V V V V V V V V V A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
EE323: DESIGN OF A BJT OP-AMP
Bias Point Ib(Q11): Ie(Q11): Ic(Q12): Ib(Q12): Ie(Q12): I(R2): Ic(Q13): Ib(Q13): Ie(Q13): Ic(Q14): Ib(Q14): Ie(Q14): Ic(Q15): Ib(Q15): Ie(Q15): Ic(Q16): Ib(Q16): Ie(Q16): Ic(Q17): Ib(Q17): Ie(Q17): I(Re5): I(Rc3): Ic(Q18): Ib(Q18): Ie(Q18): I(R3): Ic(Q19): Ib(Q19): Ie(Q19): Ic(Q20): Ib(Q20): Ie(Q20): Ic(Q21): Ib(Q21): Ie(Q21): Ic(Q22): Ib(Q22): Ie(Q22):
A PPENDIX B DC B IAS P OINT A NALYSIS CONT. SPICE Theoretical Experimental -1.9E-05 -2.0E-05 x 1.9E-03 2.0E-03 x -1.9E-03 -2.0E-03 x -1.9E-05 -2.0E-05 x 1.9E-03 2.0E-03 x 4.0E-03 4.0E-03 x 3.9E-03 4.0E-03 x 3.8E-05 4.0E-05 x -4.0E-03 -4.0E-03 x 3.9E-03 4.0E-03 4.00E-03 3.0E-05 4.0E-05 x -3.9E-03 -4.0E-03 x 3.9E-03 4.0E-03 x 3.7E-05 4.0E-05 x -3.9E-03 -4.0E-03 x 3.9E-03 4.0E-03 x 3.7E-05 4.0E-05 x -3.9E-03 -4.0E-03 x -1.2E-03 -1.1E-03 x -1.1E-05 1.1E-05 x 1.2E-03 1.1E-03 x 1.2E-03 1.1E-03 1.80E-03 1.1E-03 9.0E-04 1.70E-03 1.9E-02 2.0E-02 x 1.8E-04 2.0E-04 x -1.9E-02 -2.0E-02 x 1.1E-02 11..3e-3 x 1.9E-02 2.0E-02 x 2.2E-04 2.0E-05 x -2.0E-02 -2.0E-02 x 1.1E-02 1.1E-02 1.13E-02 1.8E-05 2.0E-05 x -1.1E-02 -1.1E-02 x 1.9E-02 2.0E-02 x 2.2E-04 2.0E-04 x -1.9E-02 -2.0E-02 x 1.9E-02 2.0E-02 x 2.2E-04 2.0E-05 x -1.9E-02 -2.0E-02 x
6
Units A A A A A A A A A A A A A Fig. 15. Negative Amplifiers A A A A A A A A A A A A Fig. 16. Non-Inverting Amplifier with a ACL of 10 A A A A TABLE II A C HARACTERISTICS OF BJT O PERATIONAL A MPLIFIER A A Characteristics SPICE Units Input Bias Current 142 nA A Input Offset Current 4 pA A Input Offset Voltages 47uV uV A ft 35 MHz fbol 60 kHz A kV SlewRate 20 us A A A
R EFERENCES [1] R. Gayakwad , Op-Amps and LInear Integrated Circuits, 3rd ed. Englewood Cliffs, New Jersey: Prentice Hall, 1993. [2] A. Hambley , Electronics, 2nd ed. Upper Saddle River, New Jersey: Prentice Hall, 2000. [3] B. Rasavi , Fundamentals of Micro-Electronics, 2nd ed. Hoboken, NJ: Wiley, 2008. [4] R. Pease(editor), M. Thompson, Analog Circuits-Chapter3, 2nd ed. Hoboken, NJ: Wiley, 2008. [5] C. Crespo, Transistor Study Guide, 1st ed. Portland, OR: OIT, 2009.
TABLE III G AIN -BANDWIDTH OF BJT O P -A MP Circuits Non-Inverting Non-Inverting Non-Inverting Non-Inverting Non-Inverting Inverting Inverting Inverting Inverting Inverting
Acl 1000 500 100 10 1 -1000 -500 -100 -10 1
fbcl 557kHz 1.2MHz 5.7MHz 14.7Mhz 26MHz 539kHz 1.2MHz 5.6MHz 14.4MHz 24MHz
Actual Gain x x x x 0.57 x x x x x
1
Design of a Discrete BJT Operational Amplifier Michael Jones, Student Member, IEEE, Audio Engineering Society
Abstract—The operational amplifier consists three basic stages. • High Impedance, Differential Input Amplifier • Voltage Amplification Stage • Single-Ended Low Impedance Output The components, and stages of an integrated circuit op-amp are direct-coupled. Direct coupling presents many challenges to the designer. These challenges will be explored, as a simple, three stage discrete BJT op-tamp will be designed, simulated, characterized, and finally implemented.
Many of the design restrictions, and challenges in analog IC design arise from limited chip size. Therefore, resistances are kept low, and the use of capacitors is limited. Other active devices, such as inductors, are impractical due to their size. Transistors, due to their small size, are called upon to provide many functions in the integrated circuit; including resistance (active-loads), current/voltage amplification, and the creation of current sources, i.e.current mirrors, for biasing. Transistors are the most numerous component in any IC. Another challenge in IC design comes from the direct coupling of transistors. Transistors must be biased so that they provide their intended functionality, while properly biasing transistors they are directly coupled to. This biasing point of a transistor is also called the quiescent operating point, Q-point, or DC operating point. A BJT transistor can be biased with a current, or a voltage. Proper biasing is one of the most important steps in the design of integrated circuits. An IC op-amp is a directcoupled high-gain amplifier, usually consisting of one or more differential amplifiers, followed by a DC level shifter, and a low impedance output stage [1]. The following paper presents the design, analysis, and implementation of a discrete BJT operational amplifier, using direct coupling, and no capacitors. II. C IRCUIT T OPOLOGY A. Differential Input Stage The first stage of the op-amp is a differential amplifier with high input impedance, see figure 1. A Darlington Pair at the input increases the input impedance by a factor of β. The input impedance of the op-amp is equal to the input impedance of the first stage. It is calculated with equation 1 (1)
A cascode current mirror was designed to sink 1mA. This current biases the first stage. The 1mA current gets divided equally between transistor pairs, Q1,2 , and Q3,4 , see Appendix A. The cascode current mirror was chosen for it’s large output impedance, ro! , see equations 2, 3. This impedance reduces the common mode gain, eq. 5, and increases the common mode rejection ration, (CMRR), eq. 6.
|VA | Ibias
ro!cascode = β(ro! ) Avdb = Acm =
I. I NTRODUCTION
Zin = 2βQ1 βQ2 (re!2 + RE1)
ro! =
re!
−Rc re! + Re
−Rc + Re + 2ro!cascode
(2) (3) (4) (5)
Avdb re! + Re + 2ro!cascode = (6) Acm re! + Re Emitter degeneration, RE1, and RE2, was used as a form of negative for this stage. The addition of these resistors reduces the gain of the stage, eq. 4, and increases the input impedance, eq. 1. However, emitter degeneration helps to reduce non-linear distortion, and increase the large-signal transfer characteristic [2], [3]. The value for RE1, and RE2 was determined using equation 7, [2]. CM RR =
Re =
40VT Ibias
(7)
A comparison of figures 2, and 3 demonstrates the effect emitter degeneration has on the linear operating range. RC1 and RC2 are used to drop a third of the supply voltage at the nodes Vout1, and Vout2. These collector resistors also affect the final gain of the stage, eq. 4. Table I lists these parameter values. The experimental output of the first stage circuit can be viewed in figure 4. B. Voltage Amplification Stage This stage is designed for large amounts of gain. An active load is used to achieve a large resistance value, eq. 2. The PNP transistors used have an early voltage, VA , equal to 120V. The transistors are being biased with 2mA; therefore, the active load is equivalent to 60kΩ. Active loads make large gains possible, without taking up too much ”real estate”. The gain of the second stage can be calculated with eq.8. A cascode current mirror was chosen to bias transistors Q9 , Q10 , Q11 , and Q12 . However, unlike the first stage, eq.9 is used to calculate the CMRR. ro! + Re)
(8)
Avds re! + Re + 2ro!cascode = Acm 2(re! + Re)
(9)
Avds = CM RR =
2(re!
VOU T 3 = (IcQ12 − IcQ10 )ro!Q12
(10)
EE323: DESIGN OF A BJT OP-AMP
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Emitter degeneration was used again to increase linearity, and reduce distortion [2]. The biasing of the output, Vout3, of this stage is not as straight forward as the biasing of the first stage’s output. The impedance the amplifier sees looking into the collector of Q12 is not the same impedance the current sees looking into the emitter of that transistor. This voltage drop can be estimated by using equation 10, [5]. This equation still gives you a ”ballpark” figure. It is also worthwhile to note that this voltage drop is current dependent. One has to keep in mind that an increase in current causes a decrease in ro’. The fine tuning of R2 allows one to see the effect that the bias current has on the operating point of V out3. Figures 5, and 6 show the experimental, and SPICE output waveforms for this stage. Both figures display output distortion.This distortion is due to the lack of headroom at Vout3. The voltage amplification stage provides a gain of ≈ 60. See table I. C. DC Level Shifter and Class A-Output Stage The last two stages of the op-amp are composed of a P N P common emitter (CE) amplifier, and a N P N emitter follower, [2]. The P N P acts as a DC level shifter, and as the last gain stage for the op-amp, eq.11, ACE =
−Rc3 re! + Re5
(11)
The +0.7V shift from V out3 to the emitter of Q17 allows the the P N P to be biased with a current of the designer’s choosing. This current, IQ17 will be: IQ17 =
V pp−VE17 RE5
A current of ≈ 1.1mA was chosen. The additional 100uA s for the base current of transistor Q18 . This base current was calculated as follows. Ibase =
Ibias βQ18
The voltage at node VC17 is selected to be ≈ +0.7V above the desired output value. Node VC17 was biased at 1V . The resistor RC3 accomplishes this biasing, and it’s value is calculated as follows: RC17 =
1V −VN N IRC3
Note: RE5 , and RC3 must be carefully selected, as each affects the biasing of Q17 , and the output voltage offset. The emitter follower, Q13 , is biased with a cascode current mirror that sinks 11.3mA of current. The emitter resistance for the N P N emitter follower is ro!Q20 . This stage is a class A output stage. An amplifier in which the transistor is on for the entire output cycle is called ”class A” [3]. This output was chosen for it’s simplicity, and it’s linearity [3]. The output node V out has a final theoretical offset of 0.3V , see Appendix A. Figure 7, and 8 shows the SPICE, and experimental output of the discrete BJT operational amplifier. It is not possible to attain an input voltage in the laboratory that is low enough to obtain an accurate open loop gain of the operation amplifier. Hence, the voltage output in fig.8 is ”railing”. The linearity of the operational amplifier can be seen in figure 9, which shows the offset of the output, at +358mV input. Figure 9 also shows
that the op-amp will behave linearly for a voltage input of -2mV to 1mV. III. C HARACTERIZATION Table II shows various characterization parameters for the simulated circuit. The input bias current can be found by measuring the base currents of transistors, Q1 , andQ3 [1]. The input offset current can be found by calculating the folllowing: Iof f set = |IBQ1 − IBQ2 |
The input offset voltage is defined as the voltage that must be applied at the input to null the output [1]. This value was found by grounding the inverting input, and sweeping the DC source of the non-inverting. The frequency response of the simulated circuit is shown in figure 10. Figure 10 was used to find the value for ft , and fBOL . It is worth noting that the fBOL for a µ741A is around 10Hz. The low fBOL for a µ741A is due to the presence of a small, ≈ 30pF , frequency compensating capacitor in the circuit [4]. The slew rate of the op-amp was tested with the circuit in figure 13. This circuit tests how fast the op-amp can track the input voltage. The slew rate is defined in equation 12. Similar to the fBOL , the slew rate is higher for an amplifier without a capacitor. Equation 13 shows the relationship between slew rate and capacitance. Capacitance reduces slew rate [4]. The value obtained during the SPICE simulation is highly dependent on the accuracy of the model for the transistors used. The accuracy of the value obtained is questionable, see table II. SR =
dVout |maximum dt
dVout I = dt C
(12)
(13)
It is interesting to view the common mode output as a function of frequency, figure 14. The CMRR of this op-amp degrades after 10kHz, at an average rate of about −20dB dec . IV. N EGATIVE F EEDBACK C IRCUITS The op-amp was placed in Inverting, and Non-Inverting circuit configurations to test it’s operation in negative , figure 15. Figure 10 displays the effect closed loop gain has on the frequency response of the op-amp. Notice, as ACL , decreases,fBCL increases. This relationship is well defined, and is termed the Gain − Bandwidth P roduct, see equation 14. ft = AOL fBOL = ACL fBCL
(14)
Figure 16 shows the simulated output of the op-amp when placed in non-inverting configuration. The design behaves, as expected. Figure 11 shows the experimental output when the circuit is configured as a non-inverting voltage follower. Table III displays the gain calculated from figure 11.
EE323: DESIGN OF A BJT OP-AMP
3
V. E XPERIMENTAL R ESULTS The op-amp circuit designed was built, and tested stage, by stage in the laboratory. The first stage performed well. The bias voltage, and currents were comparable to theoretical, and SPICE values. However, the first stage of gain was less than expected. The second stage performed as expected. Figures 5, and 6 display the similarity between simulated, and experimental results. Table I shows the gain of the second stage varies from both SPICE, and theoretical. However, the cumulative gain Avd1 × Avd2
is 505 for SPICE, and 497, for experimental. These results are very close. The last stage did show clipping, in response to the smallest input that could be obtained in the laboratory, ≈ 10mV , see figure 8. This result was expected. The experimental circuit behaved erratically when placed in negative . The circuit would work as a voltage follower; however, fine tuning of resistors RE5 , and RC5 , along with checking, and re-checking the bias points, and currents of the P N P CommonEmitter stage was required. It was not possible to obtain results for closed loop gains higher than one. These difficulties made further experimental characterization of the device nearly impossible. During troubleshooting, It was found that DC bias point of node VC17 was higher than expected. It was also found that the output of the BJT op-amp was biased at -2.8V. Standard troubleshooting measures were taken; including, checking wiring, breadboard functionality, and signal chain continuity. Additional emitter resistance was added to Q18 , in an attempt raise the DC offset at output. This resistance was shown to raise output voltage offset in SPICE; however, it did not change the offset value in the laboratory.
Fig. 1.
Discrete BJT Operational Amplifier Circuit Topology
Fig. 2.
Transfer Characteristic of First Stage without Emitter Degeneration
Fig. 3.
Transfer Characteristic of First Stage with Emitter Degeneration
VI. D ISCUSSION AND C ONCLUSION The obvious flaw in the design of this discrete operational amplifier lies in the output stage. The implementation of a CE/CC output stage is difficult. Inherent difficulties lie in choosing values for RC3, and RE5 that will create the proper bias current for the P N P , and provide the proper level shift for the desired output voltage. This type of output stage does not provide any temperature compensation. Voltage offset at the output will drift with temperature changes. Further investigation into output stage, topology and negative is required to obtain a stable operational amplifier.
TABLE I D EVICE PARAMETERS FOR BJT O PERATIONAL A MPLIFIER Device Paramaters Zin Zout Avd1 Avd2 Avd3 Total Avd Acm1 Acm2 AcmTotal CMRR
SPICE 9.50M Ω 230Ω 6.4 79 12.2 6723 -61dB -38db -77dB 153.5dB
Theoretical 21M Ω 136Ω 9.6 63.4 12.8 6513 -66dB -44dB -110dB 186dB
Experimental 20.8M Ω x 4.36 114 x 870 -14dB x x 73dB
EE323: DESIGN OF A BJT OP-AMP
Fig. 4.
Fig. 5.
Fig. 6.
4
Fig. 7.
SPICE Simulated Maximum OutputSwing of Operational Amplifier
Fig. 8.
Experimental Maximum OutputSwing of Operational Amplifier
Fig. 9.
SPICE Generated Voltage Transfer Characteristic of BJT Op-Amp
Output of Differential Input Stage
Gain and DC Offset of Voltage Amplification Stage
SPICE Simulated Output of Voltage Amplification Stage Fig. 10.
Frequency Response of BJT Operational Amplifier
EE323: DESIGN OF A BJT OP-AMP
5
A PPENDIX A DC B IAS P OINT A NALYSIS
Fig. 11.
BJT Op-Amp Configured as Non-Inverting Voltage Follower
Fig. 12.
Test Circuit used to Determine SlewRate
Fig. 13.
Output of Voltage Follower used to Determine Slew Rate
Fig. 14.
Frequency Response of Common Mode Output
Bias Point Vout1 Vout2 Vout3 Vout J1 J2 VE17 VC17 Vm1 Vm2 Vm3 Vm4 Ic(Q1): Ib(Q1): Ie(Q1): Ic(Q2): Ib(Q2): Ie(Q2): Ic(Q3): Ib(Q3): Ie(Q3): Ic(Q4): Ib(Q4): Ie(Q4): I(Rc1): I(Rc2): I(R1): Ic(Q5): Ib(Q5): Ie(Q5): Ic(Q6): Ib(Q6): Ie(Q6): Ic(Q7): Ib(Q7): Ie(Q7): Ic(Q8): Ib(Q8): Ie(Q8): Ic(Q9): Ib(Q9): Ie(Q9): Ic(Q10): Ib(Q10): Ie(Q10):
SPICE 9.98 9.97 12.84 0.36 -1.63 8.34 13.50 1.55 -13.69 14.33 -13.61 -13.52 4.64E-06 1.04E-07 -4.7E-06 4.8E-04 4.7E-06 -4.8E-04 4.6E-06 1.0E-07 -4.7E-06 4.8E-04 4.7E-06 -4.8E-04 5.0E-04 5.0E-04 1.0E-03 9.9E-04 1.0E-05 -1.0E-03 9.7E-04 1.1E-05 -9.8E-04 9.8E-04 9.9E-06 -9.9E-04 9.8E-04 9.9E-06 -9.9E-04 1.9E-03 1.8E-05 -1.9E-03 1.9E-03 2.4E-05 -1.9E-03
Theoretical 10.00 10.00 13.00 0.30 -1.40 9.30 13.70 1 -13.60 14.30 -13.60 -13.60 5.50E-04 5.00E-08 -5.0E-06 5.0E-04 5.0E-06 -5.0E-06 5.0E-04 5.0E-08 -5.0E-06 5.0E-04 5.0E-06 -5.0E-06 5.0E-04 5.0E-04 1.0E-03 1.0E-03 1.0E-05 -1.0E-03 1.0E-03 1.0E-05 -1.0E-03 1.0E-03 1.0E-05 -1.0E-03 1.0E-03 1.0E-06 -1.0E-03 2.0E-03 2.0E-05 -2.0E-03 2.0E-03 2.0E-05 -2.0E-03
Experimental 9.9 9.9 12.6 -2.8 -1.54 8.3 13.2 5.3 -13.6 14.3 -13.6 -13.6 x x x x x x x x x x x x x x x x x x 9.80E-04 x x x x x x x x x x x x x x
Units V V V V V V V V V V V V A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
EE323: DESIGN OF A BJT OP-AMP
Bias Point Ib(Q11): Ie(Q11): Ic(Q12): Ib(Q12): Ie(Q12): I(R2): Ic(Q13): Ib(Q13): Ie(Q13): Ic(Q14): Ib(Q14): Ie(Q14): Ic(Q15): Ib(Q15): Ie(Q15): Ic(Q16): Ib(Q16): Ie(Q16): Ic(Q17): Ib(Q17): Ie(Q17): I(Re5): I(Rc3): Ic(Q18): Ib(Q18): Ie(Q18): I(R3): Ic(Q19): Ib(Q19): Ie(Q19): Ic(Q20): Ib(Q20): Ie(Q20): Ic(Q21): Ib(Q21): Ie(Q21): Ic(Q22): Ib(Q22): Ie(Q22):
A PPENDIX B DC B IAS P OINT A NALYSIS CONT. SPICE Theoretical Experimental -1.9E-05 -2.0E-05 x 1.9E-03 2.0E-03 x -1.9E-03 -2.0E-03 x -1.9E-05 -2.0E-05 x 1.9E-03 2.0E-03 x 4.0E-03 4.0E-03 x 3.9E-03 4.0E-03 x 3.8E-05 4.0E-05 x -4.0E-03 -4.0E-03 x 3.9E-03 4.0E-03 4.00E-03 3.0E-05 4.0E-05 x -3.9E-03 -4.0E-03 x 3.9E-03 4.0E-03 x 3.7E-05 4.0E-05 x -3.9E-03 -4.0E-03 x 3.9E-03 4.0E-03 x 3.7E-05 4.0E-05 x -3.9E-03 -4.0E-03 x -1.2E-03 -1.1E-03 x -1.1E-05 1.1E-05 x 1.2E-03 1.1E-03 x 1.2E-03 1.1E-03 1.80E-03 1.1E-03 9.0E-04 1.70E-03 1.9E-02 2.0E-02 x 1.8E-04 2.0E-04 x -1.9E-02 -2.0E-02 x 1.1E-02 11..3e-3 x 1.9E-02 2.0E-02 x 2.2E-04 2.0E-05 x -2.0E-02 -2.0E-02 x 1.1E-02 1.1E-02 1.13E-02 1.8E-05 2.0E-05 x -1.1E-02 -1.1E-02 x 1.9E-02 2.0E-02 x 2.2E-04 2.0E-04 x -1.9E-02 -2.0E-02 x 1.9E-02 2.0E-02 x 2.2E-04 2.0E-05 x -1.9E-02 -2.0E-02 x
6
Units A A A A A A A A A A A A A Fig. 15. Negative Amplifiers A A A A A A A A A A A A Fig. 16. Non-Inverting Amplifier with a ACL of 10 A A A A TABLE II A C HARACTERISTICS OF BJT O PERATIONAL A MPLIFIER A A Characteristics SPICE Units Input Bias Current 142 nA A Input Offset Current 4 pA A Input Offset Voltages 47uV uV A ft 35 MHz fbol 60 kHz A kV SlewRate 20 us A A A
R EFERENCES [1] R. Gayakwad , Op-Amps and LInear Integrated Circuits, 3rd ed. Englewood Cliffs, New Jersey: Prentice Hall, 1993. [2] A. Hambley , Electronics, 2nd ed. Upper Saddle River, New Jersey: Prentice Hall, 2000. [3] B. Rasavi , Fundamentals of Micro-Electronics, 2nd ed. Hoboken, NJ: Wiley, 2008. [4] R. Pease(editor), M. Thompson, Analog Circuits-Chapter3, 2nd ed. Hoboken, NJ: Wiley, 2008. [5] C. Crespo, Transistor Study Guide, 1st ed. Portland, OR: OIT, 2009.
TABLE III G AIN -BANDWIDTH OF BJT O P -A MP Circuits Non-Inverting Non-Inverting Non-Inverting Non-Inverting Non-Inverting Inverting Inverting Inverting Inverting Inverting
Acl 1000 500 100 10 1 -1000 -500 -100 -10 1
fbcl 557kHz 1.2MHz 5.7MHz 14.7Mhz 26MHz 539kHz 1.2MHz 5.6MHz 14.4MHz 24MHz
Actual Gain x x x x 0.57 x x x x x
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