Apple Powerbook G4 A1085 2k4p71

12

34

R302

SOT-363 5 2 VCORE_VCC

R3491

SOT-363 4 3

R384 34 30 7

1

U_VCORE_HI_OC

0

1

R397

2

5% 1/16W MF 402 2

27.4K

1% 1/16W MF 402 2

5% 1/16W MF 402

20% 10V CERM 2 603

5

2

VCORE_SHDN_L

38

R366 14

1

INT_GPIO1_PU

5 10

VCORE_ILIM

(VCORE_GNDSNS) 11

2

34

16

MAX1717_AB_SEL

NO STUFF

5% 1/16W MF 402

V+

1

R337

38

VCORE_REF

2.2

34

VCORE_VID<0>

34

VCORE_VID<1>

38

VCORE_TON

38

1

VCORE_DH

REF

8

TON

LX

23

38

VCORE_LX

38

VCORE_CC

6

CC

DL

14

38

VCORE_DL

D0 D1 D2 D3 D4

GND

13

MIN_LINE_WIDTH=10

21

MIN_LINE_WIDTH=10

20

34

VCORE_VID<2>

MIN_LINE_WIDTH=10

19

34

VCORE_VID<3>

MIN_LINE_WIDTH=10

18

34

VCORE_VID<4>

MIN_LINE_WIDTH=10

17

MAX1717 VID CAN TAKE 3.3V TO 5.5V INPUTS

R336 C529 1 470K

5% 1/16W MF 2 402

B

38

FB 4 TIME 3 VGATE 12

39 38

R4481

R3851

1% 1/16W MF 402 2

1% 1/16W MF 402 2

66.5K

0.01UF

20% 16V CERM 2 402

12.7K

1

C512 1

C459 1UF

1

VCORE_GNDA

+5V_MAIN

100K 2 5% 1/16W MF 402

NO STUFF 1

VDAC D3 D2 D1 D0 D4=0 D4=1

A

2.00 1.95 1.90 1.85 1.80 1.75 1.70 1.65 1.60 1.55 1.50 1.45 1.40 1.35 1.30

1.275 1.250 1.225 1.200 1.175 1.150 1.125 1.100 1.075 1.050 1.025 1.000 0.975 0.950 0.925

NO U

NO U

8

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

VCORE_SEL_ON

R806

OUTPUT VOLTAGE

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

0

CRITICAL

20% 6.3V CERM 2 805

C768

2

7

38 39

R331

0.0012

1

SM1

8

U_VCORE_SLEEP 5 6 34

1% 1W MF 2512

CRITICAL

IRF7832

4

SO-8

1 2

1

Q53

IRF7832

4

CRITICAL

SO-8

3

1

1

0.0047uF

10% 25V CERM 2 402

2

D25 B540C

2 3 5% NO STUFF 1/4W MF 1210 2

1

CRITICAL

CRITICAL

CRITICAL

CRITICAL

C728 1

C734 1

C733 1

C732 1

C885 1

20% 2V 2 TANT 7343

20% 2V 2 TANT 7343

20% 2V 2 TANT 7343

20% 2V 2 TANT 7343

20% 2V 2 TANT 7343

220UF

SM

CRITICAL

220UF

220UF

CRITICAL

U_VCORE_SNUB

1

1

0.0022uF

CRITICAL

C730

1

220UF

20% 2 2V TANT 7343

1

220UF

CRITICAL

C731 220UF

C729

CRITICAL 1

220UF

20% 2 2V TANT 7343

220UF

C884 220UF

20% 2 2V TANT 7343

20% 2 2V TANT 7343

B

2

2

Keep trace fat and short!!

This allows for an offset to the ground sense to adjust the output voltage. VREF = 2.0V, HENCE VOFFSET = 2.0V * (R1/(R1+R2)) AND VCORE = VDAC + VOFFSET. 34 38

Q86

2

G

SOT-363

S

PLACE THIS SHORT AT PIN OF 1000uF CAP CLOSEST TO U

3.01K 1% 1/16W MF 2 402

R1

NOTE: R310 (R2) NO STUFFED FOR NO OFFSET CASE

XW3 SM

1

2 AB_SEL_LOW

38 34

G

NO STUFF

NO STUFF

SOT-363

S

R315

4

38 34

VCORE_GNDDIV

100K

1% 1/16W MF 402

TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION

1

RESISTOR

R321

?

1_30_VCORE

114S6343

1

RESISTOR

R321

?

1_32_VCORE

NO STUFF

R312 VCORE_GNDSNS

1

100

1% 1/16W MF 402

FOR V-STEP: Lo/Slow 0

1

1

>= 100K PD

0

1

<= 1K PD

0

0

J5

TABLE_5_ITEM

114S4023

38 34

1

NO STUFF M-ST-SM-52465-1217

TABLE_5_ITEM

>= 100K PU

FMAX CONNECTOR CRITICAL

2.05K2

1

R808

<= 1K PU

1 VCORE_SNS

ROUTE AS DIFFERENTIAL PAIR

2N7002DW

A/B_ =

2 38

Q86

D

5% 1/16W MF 2 402

VCORE_GNDSNS

3

1

2

1

12

VCORE_VID<0>

34

VCORE_GNDDIV_TEST

2

11

VCORE_VID<1>

34

VCORE_GNDSNS_TEST

3

10

VCORE_VID<2>

34

30

+3V_PMU_RESET

4

9

VCORE_VID<3>

34

30 23 22

SOFT_PWR_ON_L

5

8

VCORE_VID<4>

34

6

VCORE SUPPLY NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

7

NC (RFU)

When A/B_ is high (fast): D4-D0 read as-is When A/B_ is low (slow): <=1K-ohm -> 0 >=100K-ohm -> 1

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

If all pull-ups are >=100K and all pull-downs are <=1K, V A = V B .

APPLE COMPUTER INC.

DRAWING NUMBER

6

SCALE

5

4

3

2

REV.

051-6598 01

D

SHT NONE

7

10UF

20% 6.3V CERM 2 805

CRITICAL

R321

2N7002DW

5

Hi/Fast

C687 1

1

10UF

20% 6.3V CERM 2 805

OMIT

5% 1/16W MF 402

D<4..0>

C3

1

10UF

20% 6.3V CERM 2 805

1

R807 1

C4

1

10UF

GROUND SENSE VOLTAGE DIVIDER

R2

VCORE_GNDDIV

D

MAX1717_AB_SEL

0

20% 6.3V CERM 2 805

6

2

5% 1/16W MF 402 34

1% 1/16W MF 2 603

1% 1/16W MF 2 402

5 6

Connect MAX1717 GND pin 13 to GND at bottom-side FET

162K

1.5K

8

NO STUFF 10% 50V CERM 603

R376

R809

6 7

C764

1

1 VCORE_SEL_OFF_PU

10UF

20% 6.3V CERM 2 805


L36

2.2

VCORE_OFFSET

R805 1

C285

U_VCORE_SLEEP_F

XW7 SM 1

C695 1

1

10UF

C

5% 1/16W MF 402

20% 50V CERM 2 402

C6

1

20% 6.3V CERM 2 805

XW15 SM

2 3

Q55

2

20% 6.3V CERM 2 805

SO-8-PWRPK

CRITICAL

SO-8

2

100

10UF

20% 6.3V CERM 2 805

10UF

SI7860DP

Q54

3

C116

1

20% 6.3V CERM 2 805

20% 6.3V CERM 2 805


5

R415 1

10UF

Q49 4

1

7 8

1 2

C680 1

1

10UF

20% 6.3V CERM 2 805

CRITICAL

3

IRF7832

XW5 SM

14 38

C13

10UF

10UF

R7321

0.001UF

5% 1/16W MF 402 2

6

4

C521

390K

5

20% 25V 2 CERM 603

VCORE_TIME 38 VCORE_VGATE

C693 1

1.2UH-18.3A

0.1UF

VCORE_FB

R434

5% 25V CERM 2 402

20% 10V 2 CERM 603

2

C7

1

10UF

20% 6.3V CERM 2 805

C679 1

20% 2 16V TANT CASE-D

VCORE_GND

1

220PF

1

C274

1

10UF

CRITICAL

C518

1 1

8.2UF


SO-8-PWRPK

10% 25V 2 CERM 402

470K

5% 1/16W MF 2 402

8.2UF


SI7860DP

0.0047uF

5% 1/16W MF 603

9

C674

20% 6.3V CERM 2 805

C455

1

20% 6.3V 2 CERM 805

C445

NO STUFF 1

R429 VCORE_BST 2

10UF

20% 6.3V 2 CERM 805

CRITICAL

1

Q50

38 22 BST DH 24

C234

10UF

20% 6.3V 2 CERM 805

1

5

4

CRITICAL

1

8.2UF

C444

5

VCORE_VPLUS

10UF

20% 6.3V 2 CERM 805

1

C430


CRITICAL

1

C441 8.2UF

8.2UF

VDD

SKP/SDN FBS ILIM GNDS A/B

8.2UF


CRITICAL

1


U20 QSOP

C699

1

CRITICAL

1

C443

CRITICAL

MAX1717

(VCORE_SNS)

0

8.2UF

C432

15

VCC

1UF

CRITICAL

1

C431


CRITICAL

1

MBR0530

38

7

D2 SM

2

20% 2 10V CERM 603

R4071 C507 1 0

+3V_MAIN

C498 1UF

5% 1/16W MF 402 2

C NO STUFF

1

20

C5

1

10UF

10UF

2

DCDC_EN

1

PLACE C423 CLOSE TO PINS 15 & 13!!

C689

1

C682 1

CRITICAL

1

C427 8.2UF

VCORE_BOOST

39 33 29 19

C2


38

D

U_VCORE_SLEEP

20% 6.3V 2 CERM 805

CRITICAL

+5V_MAIN

DP2

39 38 34 6 5

20% 6.3V CERM 2 805

DP2

BAS16TW

5% 1/16W MF 2 402

+PBUS

BAS16TW SLEEP_L_LS5

0

Keep trace fat (40-100 mils) and short!!

1

35 33 27 19

R292

SEL = 0; Y1=A1 SEL = 1; Y1=B1

5% 1/16W MF 2 402

1

10UF

1K

5% 1/16W MF 2 402

5% 1/16W MF 2 402

34

NO_4XVCORE

0

8

1

0

R290

1/16W MF 2 402

VCORE_VID<4>

GND

NO STUFF

NO STUFF

1

CRITICAL

15

VCORE_MUX_EN

39

NO STUFF

NO STUFF

Q17

1

U_VCORE_SEQ

34

5% 1/16W MF 402

2N3904 3

0

1

U_VCORE_HI_OC

10K

5% 1/16W MF 402 2

R288

U11 PI3B3257 A1 QSOP Y1 B1 Y2 A2 B2 A3 Y3 B3 A4 Y4 B4

2

34

U_VCORE_SEQ_L

VCC

SYM_VER-2

3 1

20% 10V 2 CERM 402

16

5% 1/16W MF 2 402

34

NO_4XVCORE VCORE_FAST<2> 34 1 NO_4XVCORE 0 VCORE_FAST<3> 34 5% 1 1/16W NO_4XVCORE MF 0 VCORE_FAST<4> 402 2 5% 1

0.1UF

10K

5% 1/16W MF 2 402

100K

100K

R322

0

5% 1/16W MF 2 402

5% 1/16W MF 2 402

1

VCORE_SLOW<1>

R356

R398

1

R304

VCORE_FAST<1>

C439

1 1

5% 1/16W MF 2 402

1

1

5% 1/16W MF 402 2

MAXBUS_SLEEP

NO STUFF

NO STUFF

1

1

NO STUFF

1 1 R328 1R324 R297 R314 470K 0 0

(approx. 7ms delay)

3

U core follows U I/O voltage

OF

34 44 1

A

8

6

7

2

3

4

5

1

+1_5V_SLEEP LOADS 1) AGP I/O - IF USING D3COLD 2) MAXBUS I/O - IF 1.5V INTERFACE

1.5V/2.5V SWITCHER

+1_5V_MAIN

R715

+1_5V_SLEEP

2

+1_5V_SLEEP_VIN

5% 1/16W MF 603 NO STUFF

1

R712

2

1

0

5

2

+2_5V_MAIN

THERE’S 100K PULL-UP ON PG 31 ALREADY

6

5% 1/16W MF 603

1) FBCORE/FBIO IF USING D3COLD 2) INTREPID MEMORY I/O

3

1_5V_SLEEP_EN_L

1

R461

4

100K

C723 1

1

10UF

5% 1/16W MF 402 2

C726 2200pF

20% 6.3V CERM 2 805

5% 50V 2 CERM 603

R480 20

2

NO STUFF

38

MAX1715_VCC

DP3

+5V_MAIN

20% 2 10V CERM 805

5% 1/16W MF 2 402

SOT-363 6 1

1

1

R455

R607

100K

33

DCDC_EN_L

1

330K 2

5% 1/16W MF 2 402

1

MAX1715_ON_RC

G

3

1

C531

5% 1/16W MF 2 402

MAX1715_TON

2_5V_ILIM

38

1_5V_ILIM

+PBUS

2

R4181

0.01UF

5

SLEEP_L_LS5_INV

20

VCC

VDD

35 38

33 19 27 34

SLEEP_L_LS5

5% 1/16W MF 402

2

1

G

C886

1

R493

20% 25V CERM 2 1206

1

1_5V_BOOST

38

8

7

6 5

1

IRF7805

C575

38

38

3 2

38

1

2

38

8

5.11K

C740

1

10UF

C751

1

150UF

20% 2 6.3V CERM 805

C745 150UF

20% 2 6.3V TANT SMD-1

OUT1 PGOOD REF

OUT2 14

FB1 AGND

FB2 13 THRML

SKIP

8

IRF7811W

4

SO-8

D23 SM

38

1

MBRS130LT3

3

2

1

1 2

1

C908 0.0022UF 10% OMIT 50V XW6 CERM SM 402

2

38 35

1

2_5V_BST

4.7

2

38

C582 4.7UF

C

2_5V_BOOST

5% 1/16W MF 603 1

5

C580

6 7

8

0.1UF

CRITICAL

20% 25V 2 CERM 603

MAX1715_GND 38

Q69 IRF7805

4

2_5V_DH

SM

+2_5V_MAIN

CRITICAL

6

1 MAX1715_FB2

35

38

L45

4.7UH

2 3 1

2_5V_LX

2 SM4 1

R616

29 5

6 7

8

15.4K

1

R420

POSCAPS

CRITICAL

0

38

2

SO-8

C499

1

1UF

C907

C782 150UF

20% 2 6.3V TANT SMD-1

POSCAPS

POSCAPS 1

1

C780 150UF

C788 150UF

20% 2 6.3V TANT SMD-1

20% 2 6.3V TANT SMD-1

1

35

1

R672 10K

1% 1/16W MF 2 402

2 3

20% 2 16V CERM 402

MAX1715_GND

1% 1/16W MF 2 402 MAX1715_FB2

1

0.022UF

20% 10V 2 CERM 603

20% 6.3V 2 CERM 805

MBRS130LT3

NO STUFF

1

10UF

D33 SM

IRF7811W

4

2_5V_DL

C809

1

Q68

5% 1/16W MF 2 402

1_5V_DL

NO STUFF

5% 1/16W MF 402

R479 38

5% 1/16W MF 402 2

1

B

TON

1 7

1000PF

10% 25V 2 X7R 402

20% 2 25V CERM 1206

20% 25V 2 CERM 1206

16

22

R4221

Q56

35 38

R424

1% 1/16W MF 2 402

NC

18

19

2

CRITICAL

1

10K

NC

28

DL2

1_5V_FB

5

23

0

2

20% 2 6.3V TANT SMD-1

7 6

LX2

NC

PGND

9

35 38

BST2

15

1

2

5% 50V CERM 603

C888

1

100K 2

CRITICAL

C559 4.7UF

+2_5V_MAIN

DL1

MAX1715_REF

1_5V_LX

V+ NC_15 NC_23 NC_28

5

NO STUFF

R425

1

LX1

1_5V_2_5V_OK

1

POSCAPS

DH1 CRITICAL DH2 17

27

1_5V_DH

SM4

POSCAPS

26

24

4

SM

4.7UH

1% 1/16W MF 2 402 1_5V_FB

BST1

+1_5V_MAIN

L35

1

1_5V_BST

38

20% 25V 2 CERM 603

Q57 CRITICAL

2

0.1UF

CRITICAL

+1_5V_MAIN

4.7

5% 1/16W MF 603

1

1000PF

10% 2 25V X7R 402

25

10

4.7UF

20% 25V CERM 2 1206

11

12

C519

4.7UF

SOT-363

S

CRITICAL

C544 1

2N7002DW

100K 2 1

CRITICAL 1 4

ILIM1 ILIM2 ON1 ON2

SLEEP_L_LS5_INV 1

38

QSOP

Q82

D

R417

MAX1715_SKIP

MAX1715 3

4

6

35

U22

SOT-363

S

CRITICAL

SLEEP_L_LS5_NET

C

G

1

NO STUFF

R611

21

+PBUS

5 8

C709 NO STUFF

2N7002DW

35

1

10UF

2_5V_SLEEP_PWREN_L

158K

MAX1715_GND

C705

TSSOP

1

2200pF +PBUS

1% 1/16W MF 2 402

SI6467BDQ

4

20% 6.3V CERM 2 805

R423

1% 1/16W MF 402 2

Q85

100K 2 5% 1/16W MF 402

1

158K

20% 16V 2 CERM 402

Q82

D

1

SLEEP

39 35 33 30 25 23

SM

S

38

5% 1/16W 5% MF 1/16W 402 MF 402 DIODE PROVIDE PROVIDE QUICK SHUT-DOWN 2 POWER DOWN DELAY 1.5MS TO 3.5MS 1_5V_SLEEP_EN_L 35

CRITICAL

0 38

7

R709

6) PCI1510 CORE

R419

Q19

6

5) CLOCK SLEWING I/O

1

2N7002

100K

2 3

4) DDR MUXES

20% 2 10V CERM 805

NO STUFF

3 D

R450

3) DDR SODIMMS - CORE/IO

C603 2.2UF

2.2UF

0

BAS16TW

2) GIGABIT ETHERNET - AVDDL 1

C581

1

R421

3V_5V_OK

D

1) MAP31 - FBCORE/FBIO IF USING D3HOT

1

5% 1/16W MF 402

1 35 33

+2_5V_SLEEP

+2_5V_MAIN LOADS

35

DP3

D

33

+2_5V_SLEEP LOADS

+5V_MAIN

1) INTREPID CORE 2) AGP I/O IF USING D3HOT

SOT-363 4 3

+1_5V_LDO

TSOP

BAS16TW

38

+1_5V_MAIN LOADS

Q46

SI3446DV

DP3

38

SOT-363 5 2

0

BAS16TW

1

B

+1_8V_MAIN

CHANGE R424 BACK TO 10K, 1%, AND STUFF 5.11K FOR 1.5V OPERATION CONNECTING 1_5V_FB TO GND, FORCES 1.8V OUTPUT

1.8V SWITCHER

+3V_MAIN

+1_8V_SLEEP

+1_8V_MAIN LOADS

2

3 6

7

1) INTREPID PLLS

CRITICAL

Q84

R190 39 35 33 30 25 23

SLEEP

1

CONTINUOUS MODE

22UF

20% 6.3V CERM 2 1206

20% 6.3V 2 CERM 1206

1

1

R727 R797 4.7M

5% 1/16W MF 2 402

5% 1/16W MF 2 402

7

TSSOP RT PGOOD 2 RUN/SS

1

R810

3

A

Q83

D

2N7002DW

35 33

3V_5V_OK

5

G

SOT-363

S

CRITICAL

R803

15K 1

C890 100PF

5% 50V 2 CERM 402

4

0

1% 1/16W MF 2 402 LTC3412_ITH_RC 1

1

C892 470PF

10% 50V 2 CERM 402

5% 1/16W MF 2 402

1% 1/16W MF 2 402

R799

1% 1/16W MF 2 402

R800 75K

5% 2 25V CERM 603

10 1_8V_SW 1 11 14

3) U PLL Config Straps 4) OPTIONAL VIDEO MEMORY (M10 PRO ONLY)

20% 6.3V 2 CERM 805

+1_8V_MAIN

C235

2200pF 2

1XW11 2

+1_8V_MAIN_LX_F

SM

NO STUFF

R610

JUMPER OPEN 35

1

2

1_8V_SLEEP_PWREN_L

SLEEP_L_LS5_INV 1

100K 2 5% 1/16W MF 402

15

VFB

110K

1

1000PF

8

10UF

OMIT

1.0UH-3.5A

THERM SGND PGND PAD

1

LTC3412_VFB_DIV

C683

5

C276 1

232K

L75

C894

1

5% NO STUFF 50V 1

C887

1000PF

CERM 603

10% 25V 2 X7R 402

1.5V/1.8V/2.5V SUPPLIES

22UF

17

R798

R627

4

LTC3412_VFB

1 1

1

38

SW

8

SOT-363

S

6

BURST MODE NO STUFF

2N7002DW

ITH SYNC/MODE

13

Q83

D G

LTC3412_PGOOD

5% 2 50V CERM 402

1

CRITICAL 3

LTC3412_ITH LTC3412_SYNC

6

12

2

3V_5V_OK_INV

C893 22PF

5% 1/16W MF 2 402

U58 5

1

100K

SVIN PVIN LTC3412_RT LTC3412_RUNSS

5% 1/16W MF 2 402

1) MPC7450 - MAXBUS I/O - IF 1.8V INTERFACE 1

2) U JTAG & MaxBus Pull-ups

R802

LTC3412

100K

+1_8V_SLEEP LOADS

TSSOP

1

0

16

1

9

22UF

C93

SI6467BDQ

4

5% 1/16W MF 402

1

C891

1

100K 2

1 1

C677 22UF

R801

20% 6.3V 2 CERM 1206

1% 1/16W MF 2 402

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

OMIT

1% 1/16W MF 2 402

II NOT TO REPRODUCE OR COPY IT

XW1 SM

LTC3412_GND

1

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 2

SIZE

APPLE COMPUTER INC.

D

DRAWING NUMBER

SHT NONE

7

6

5

4

3

2

REV.

051-6598

SCALE

8

A

NOTICE OF PROPRIETARY PROPERTY

20% 2 6.3V CERM 1206

309K

OF

01

35 44 1

8 SIG_NAME

MAX_VIAS

U_AACK_L

MAXBUS

STUB_LENGTH 250.0000

U_ADDR<0..31>

5

DIGITAL SIGNALS

58

INT_UFB_OUT

3

10 MIL SPACING

8

INT_UFB_OUT_SHORT

3

10 MIL SPACING

8

5 8

INT_UFB_OUT_NORM

3

10 MIL SPACING

8

5 8

INT_UFB_IN_NORM

3

10 MIL SPACING

8

3

5

250.0000

U_DATA<0..31>

5

250

83 MHZ

6 8

INT_UFB_LONG

U_DATA<32..63>

5

250

83 MHZ

6 8

INT_UFB_IN

U_DBG_L

5

250.0000

5 8

SYSCLK_DDRCLK_A0_UF

U_DTI<0..2>

5

250

10 MIL SPACING

5 8

10 MIL SPACING 250.0000 5

10 MIL SPACING

5 8

250.0000

5 8

250.0000

10 MIL SPACING

5 8

250.0000

10 MIL SPACING

5 8

U_QREQ_L

250.0000

10 MIL SPACING

5 8

U_TA_L

250.0000

10 MIL SPACING

5 8

250.0000

10 MIL SPACING

5 8

5

5

U_TEA_L

250.0000

U_TS_L

250.0000

5 8

10 MIL SPACING

5 8

U_TSIZ<0..2>

5

250

5 8

U_TT<0..4>

5

250

5 8

U_WT_L

5

250.0000

5 8

MEM_DATA<7..0>

4

RAM_DATA_A<7..0>

4

RAM_DATA_B<7..0>

4

200

167 MHZ

200 200 TOTAL LENGTH CONTROLLED BY SPREADSHEET 200

9 10

167 MHZ

10 11

167 MHZ

10 11 9 10

RAM_DQS_A<0>

4

200

10 11

RAM_DQS_B<0>

4

200

10 11

MEM_DQM<0>

4

200

9 10

4

200

10 11

RAM_DQM_B<0>

4

200

MEM_DATA<15..8>

4

200

167 MHZ

9 10

RAM_DATA_A<15..8>

4

200

167 MHZ

10 11

RAM_DATA_B<15..8>

4

MEM_DQS<1>

4

RAM_DQS_A<1>

4

200

10 11

RAM_DQS_B<1>

4

200

10 11

200

9 10

10 11

200 TOTAL LENGTH CONTROLLED BY SPREADSHEET 200

167 MHZ

4

200

10 11

4

200

10 11

MEM_DATA<31..16>

4

200

167 MHZ

200

167 MHZ

4

200 TOTAL LENGTH CONTROLLED BY SPREADSHEET 4 200

RAM_DQS_A<3..2>

4

200

167 MHZ

10 11

167 MHZ

9 10

167 MHZ

200

167 MHZ

10 11

4

200

167 MHZ

9 10

RAM_DQM_A<3..2>

4

200

167 MHZ

10 11

RAM_DQM_B<3..2>

4

200

167 MHZ

10 11

MEM_DATA<47..32>

4

200

167 MHZ

9 10

RAM_DATA_A<47..32>

4

200

167 MHZ

10 11


167 MHZ

10 11

167 MHZ

9 10

4

167 MHZ

10 11

4

RAM_DQS_B<5..4>

4

200 200

167 MHZ

4

200

167 MHZ

9 10

RAM_DQM_A<5..4>

4

200

167 MHZ

10 11

4

200

167 MHZ

10 11

MEM_DATA<55..48>

4

RAM_DATA_A<55..48>

4

RAM_DATA_B<55..48>

4

MEM_DQS<6>

4

RAM_DQS_A<6> RAM_DQS_B<6>

4

MEM_DQM<6> RAM_DQM_A<6>

4

RAM_DQM_B<6>

4

200

167 MHZ

9 10

200

167 MHZ

10 11

167 MHZ

10 11

200 TOTAL LENGTH CONTROLLED BY SPREADSHEET 200

200

167 MHZ

10 11

200

10 11

200

9 10

200

10 11

RAM_DQM_B<7>

4

200

10 11

6 4

RAM_CS_L<3..0>

6

MEM_CKE<3..0>

4

RAM_CKE<3..0>

6

MEM_RAS_L

4

RAM_RAS_L

83 MHZ 200

200

3

200.0000

10 MIL SPACING

9

3

200.0000

10 MIL SPACING

9

3

200.0000

10 MIL SPACING

9 11

200.0000

10 MIL SPACING

9 11

200.0000

10 MIL SPACING

9 11

200.0000

10 MIL SPACING

9 11

SYSCLK_DDRCLK_A0

DDRCLK_A0

SYSCLK_DDRCLK_A0_L

DDRCLK_A0

SYSCLK_DDRCLK_A1

DDRCLK_A1

SYSCLK_DDRCLK_A1_L

DDRCLK_A1

SYSCLK_DDRCLK_B0

DDRCLK_B0

3

200.0000

10 MIL SPACING

9 11

SYSCLK_DDRCLK_B0_L

DDRCLK_B0

3

200.0000

10 MIL SPACING

9 11

SYSCLK_DDRCLK_B1

DDRCLK_B1

3

200.0000

10 MIL SPACING

9 11

SYSCLK_DDRCLK_B1_L

DDRCLK_B1

3

200.0000

10 MIL SPACING

9 11

3

200.0000

10 MIL SPACING

14

200.0000

10 MIL SPACING

14

200.0000

10 MIL SPACING

12

200.0000

10 MIL SPACING

12 18

200.0000

10 MIL SPACING

12

200.0000

10 MIL SPACING

12

200.0000

10 MIL SPACING

12

200.0000

10 MIL SPACING

12 17

200.0000

3

4

4 SHOULD BE AT MOST 4 VIAS FOR CLK

6

SHOULD BE AT MOST 4 VIAS FOR CLK

6

SHOULD BE AT MOST 4 VIAS FOR CLK

6

3

MAP31

10 MIL SPACING

12

200.0000

10 MIL SPACING

12 24 39

200.0000

10 MIL SPACING

12

200.0000

10 MIL SPACING

12 26

200.0000

10 MIL SPACING

12

200.0000

10 MIL SPACING

12

CRYSTALS

GPU_CLK27M_OUT

10 MIL SPACING

GPU_CLK27M_UF

10 MIL SPACING

GPU_SSCLK_UF

10 MIL SPACING

GPU_SSCLK_IN

10 MIL SPACING

GPU_FBCLK0

10 MIL SPACING

GPU_FBCLK0_L

10 MIL SPACING

GPU_FBCLK1

10 MIL SPACING

GPU_FBCLK1_L

10 MIL SPACING

GPU_DVO_CLKP

10 MIL SPACING

CLK27M_GPU_XOUT

10 MIL SPACING

CLK27M_XTAL_IN

10 MIL SPACING

CLK27M_GPU_XIN

10 MIL SPACING

CLK18M_INT_XIN

10 MIL SPACING

14

CLK18M_INT_XOUT

10 MIL SPACING

14

CLK18M_XTAL_IN

10 MIL SPACING

14

CLK18M_INT_EXT

10 MIL SPACING

14

CLK25M_ENET_XIN

10 MIL SPACING

27

CLK25M_ENET_XOUT

10 MIL SPACING

27

10 MIL SPACING

26

10 MIL SPACING

26

NEC_XT1 THERE’S ANOTHER 280MIL LEG

NEC_XT2 SND_SCLK

SOUND

7

200.0000

10 MIL SPACING

14 25 39

200.0000

10 MIL SPACING

14 25 39

CLKENET_PHY_RX

200.0000

CLKENET_LINK_RX

3

200.0000

CLKENET_PHY_GBE_REF CLKENET_LINK_GBE_REF

3

200.0000

CLKENET_PHY_TX

13 27 27

10 MIL SPACING

13 27

200.0000

CLKENET_LINK_TX

5

200.0000

CLKENET_LINK_GTX

27

10 MIL SPACING

13 27

200.0000

CLKENET_PHY_GTX

FIREWIRE

9

3

200.0000

CLKFW_PHY_PCLK

13

10 MIL SPACING

13 27

200.0000

28

CLKFW_LINK_PCLK

3

200.0000

10 MIL SPACING

13 28

CLKFW_PHY_LCLK

3

200.0000

10 MIL SPACING

13 28

CLKFW_LINK_LCLK

200.0000

FW_XI

200.0000

10 MIL SPACING

28

FW_OSC

200.0000

10 MIL SPACING

28

13

SIGNAL CONSTRAINTS - PAGE 1

9 11 9

200


9 11 9

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

9 11 9

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

9 11

II NOT TO REPRODUCE OR COPY IT

9

200.0000

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

9 11

MEM_MUXSEL_H<1..0>

3

9 10

MEM_MUXSEL_L<1..0>

3

9 10

RAM_MUXSEL_H

5

10

RAM_MUXSEL_L

5

10

7

B

27

10 MIL SPACING

200.0000

SIZE

APPLE COMPUTER INC.

D

DRAWING NUMBER

6

SCALE

5

4

3

2

REV.

051-6598 SHT NONE

8

C

19 20

SND_CLKOUT

9

200

4

RAM_WE_L

9

9 11

200.0000

MEM_WE_L

9

10 MIL SPACING

9

4

RAM_CAS_L

10 MIL SPACING

200.0000

9 11

200.0000

MEM_CAS_L

200.0000

3

D

9 10

200

4

MEM_CS_L<3..0>

3

SYSCLK_DDRCLK_B0_L_UF

INT_PCI_FB_IN

10 11

RAM_DQM_A<7>

RAM_BA<1..0>

SYSCLK_DDRCLK_B0_UF

INT_PCI_FB_OUT

10 11


4

9

CLK33M_USB2

10 11

4

6

10 MIL SPACING

CLK33M_AIRPORT_UF

200

10 11

MEM_BA<1..0>

200.0000

CLK33M_USB2_UF

MARVELL

167 MHZ

RAM_ADDR<12..0>

9

3

CLK33M_AIRPORT

ETHERNET

200

4

10 MIL SPACING

CLK33M_CBUS

9 10

4

MEM_ADDR<12..0>

200.0000

INT_AGP_FB_IN

10 11

RAM_DATA_A<63..56>

4

3

SYSCLK_DDRCLK_A1_L_UF

CLK33M_CBUS_UF

200

9 10

MEM_DQM<7>

9

SYSCLK_DDRCLK_A1_UF

INT_AGP_FB_OUT

200

167 MHZ

RAM_DQS_B<7>

10 MIL SPACING

CLK66M_GPU_AGP

10 11

200

RAM_DQS_A<7>

200.0000

CLK66M_GPU_AGP_UF

200

4

MEM_DQS<7>

3

9 10

MEM_DATA<63..56>

RAM_DATA_B<63..56>

9

SYSCLK_DDRCLK_A0_L_UF

INT_REF_CLK_IN

10 11

MEM_DQM<5..4>

RAM_DQM_B<5..4>

10 MIL SPACING

INT_REF_CLK_OUT

10 11

4

RAM_DQS_A<5..4>

200.0000

SYSCLK_DDRCLK_B1_L_UF

10 11

MEM_DQM<3..2>

MEM_DQS<5..4>

8

3

SYSCLK_DDRCLK_B1_UF

9 10

RAM_DQS_B<3..2>

RAM_DATA_B<47..32>

8

10 MIL SPACING

10 11

RAM_DQM_B<1>

4

10 MIL SPACING 200.0000

9 10

RAM_DQM_A<1>

MEM_DQS<3..2>

A

8

10 MIL SPACING

5 8

RAM_DATA_B<31..16>

CONTROL

200.0000

5 8

RAM_DATA_A<31..16>

ADDR

4

PULSE PARAM

10 MIL SPACING

10 MIL SPACING

MEM_DQM<1>

GROUP 7

SYSCLK_U

NET_SPACING_TYPE

10 MIL SPACING

RAM_DQM_A<0>

GROUP 6

STUB_LENGTH

10 MIL SPACING

MEM_DQS<0>

B

MAX EXPOSED LENGTH

250.0000

U_TBST_L

GROUP 4/5

5 8

MAX VIAS

250.0000

U_QACK_L

DDR RAM

83 MHZ

SIG_NAME SYSCLK_U_UF

250.0000

U_HIT_L

GROUP 2/3

GROUP

INTREPID CLOCKS

5 8

U_BR_L

U_GBL_L

GROUP 1

PULSE_PARAM

U_BG_L

U_DRDY_L

C

NO_TEST

10 MIL SPACING

250

U_DRDY_L_UF

GROUP 0

NET_SPACING_TYPE

1

U_ARTRY_L

U_CI_L

D

MAX_EXPOSED_LENGTH

2

3

4

5

CLOCK LINE CONSTRAINTS

GROUP

6

7

OF

01

36 44 1

A

8 GROUP

SIG_NAME

AGP

D

Digital Signals (cont’d)

AGP BYTES 0-1

AGP BYTES 2-3

6

7 DELAY_RULE

MAX_VIAS MAX_EXPOSED_LENGTH STUB_LENGTH

GROUP 100

66 MHz

12 18

AGP_CBE<1..0>

5

100

66 MHz

12 18

AGP_AD_STB<0>

5

100

8 MIL SPACING

12 18

AGP_AD_STB_L<0>

5

100

8 MIL SPACING

12 18

AGP_AD<31..16>

5 5 5

AGP_AD_STB_L<1> AGP_SBA<7..0>

5

AGP_SB_STB AGP_SB_STB_L

5

AGP_FRAME_L

AGP_TRDY_L

6

AGP_DEVSEL_L AGP_STOP_L

6

AGP_PAR

100

66 MHz

6

8 MIL SPACING

12 18

100

8 MIL SPACING

12 18

66 MHz

100.0000

8 MIL SPACING

12 18

100.0000

8 MIL SPACING

12 18 12 18

250.0000

12 18

250.0000

12 18

250.0000

12 18

250.0000

12 18 12 18

285.0000

12 18

AGP_GNT_L

250.0000

12 18

5

250.0000

12 18

250

19 20

GPU_DVO_HSYNC

19 20

GPU_DVO_VSYNC

19 20

MDI_P<1>

ENET_MDI1

OF PHYSICAL CONSTRAINTS

MDI_M<2>

ENET_MDI2

AROUND MARVELL PHY

MDI_P<2>

ENET_MDI2

MDI_M<3>

ENET_MDI3

MDI_P<3>

ENET_MDI3

RJ45_DN<0>

RJ45_DP0

10 MIL SPACING

27 39

RJ45_DP<0>

RJ45_DP0

10 MIL SPACING

27 39

RJ45_DN<1>

RJ45_DP1

10 MIL SPACING

27 39

RJ45_DP<1>

RJ45_DP1

10 MIL SPACING

27 39

RJ45_DN<2>

RJ45_DP2

10 MIL SPACING

27 39

RJ45_DP<2>

RJ45_DP2

10 MIL SPACING

27 39

RJ45_DN<3>

RJ45_DP3

10 MIL SPACING

27 39

RJ45_DP<3>

RJ45_DP3

27 39

FW_TPA0N

FW_TPA0

FW_TPA0P

FW_TPA0

FW_TPB0N

FW_TPB0

FW_TPB0P

FW_TPB0

FW_TPI0N

FW_TPI0

FW_TPI0P

FW_TPI0

FW_TPO0N

FW_TPO0

10 MIL SPACING MIN_LINE_WIDTH=3.4 10 MIL SPACING MIN_LINE_WIDTH=3.4 10 MIL SPACING MIN_LINE_WIDTH=3.4 10 MIL SPACING MIN_LINE_WIDTH=3.4 10 MIL SPACING MIN_LINE_WIDTH=3.4 10 MIL SPACING MIN_LINE_WIDTH=3.4 10 MIL SPACING MIN_LINE_WIDTH=3.4 10 MIL SPACING MIN_LINE_WIDTH=3.4 10 MIL SPACING MIN_LINE_WIDTH=3.4 10 MIL SPACING MIN_LINE_WIDTH=3.4 10 MIL SPACING MIN_LINE_WIDTH=3.4 10 MIL SPACING MIN_LINE_WIDTH=3.4 10 MIL SPACING MIN_LINE_WIDTH=3.4 10 MIL SPACING MIN_LINE_WIDTH=3.4 10 MIL SPACING MIN_LINE_WIDTH=3.4 10 MIL SPACING MIN_LINE_WIDTH=3.4 10 MIL SPACING

27 27

FW_TPA1

500.0000

PCI_FRAME_L

MIN_DAISY_CHAIN

12 17 24 26 39

FW_TPA1P

FW_TPA1

500.0000

PCI_IRDY_L

MIN_DAISY_CHAIN

12 17 24 26 39

FW_TPB1N

FW_TPB1

500.0000

PCI_TRDY_L

MIN_DAISY_CHAIN

12 17 24 26 39

FW_TPB1P

FW_TPB1

500.0000

PCI_DEVSEL_L

MIN_DAISY_CHAIN

12 17 24 26 39

FW_TPI1N

FW_TPI1

PCI_STOP_L

MIN_DAISY_CHAIN

12 17 24 26 39

FW_TPI1P

FW_TPI1

12 17 24 26 39

FW_TPO1N

FW_TPO1

FW_TPO1P

FW_TPO1

100 MHZ

NEED TO MATCH DELAY TO 250 200

13 24 13 24

LVDS LOWER

27

27

FW_TPO0

MIN_DAISY_CHAIN

27

27

FW_TPA1N

200

27

27

12 17 24 26 39

28 29 28 29 28 29 28 29

28 29 28 29 28 29 28 29

29 39

CLKLVDS_L

10 MIL SPACING

4

19 22 39

CLKLVDS_LP

CLKLVDS_L

10 MIL SPACING

4

19 22 39

100 MHZ

13 24

LVDS_L0N

LVDS_L0

10 MIL SPACING

19 22 39

200

100 MHZ

13 24

LVDS_L0P

LVDS_L0

10 MIL SPACING

19 22 39

200.0000

13 24

LVDS_L1N

LVDS_L1

10 MIL SPACING

19 22 39

200.0000

13 24

LVDS_L1P

LVDS_L1

10 MIL SPACING

19 22 39

200.0000

13 24

LVDS_L2N

UIDE_DMACK_L

200.0000

13 24

UIDE_CS0_L

200.0000

13 24

200.0000 200.0000 200.0000 200.0000

10 MIL SPACING

UIDE_INTRQ HD_DATA<15..0>

5

HD_ADDR<2..0>

5

HD_RESET_L

5

HD_DIOW_L

5

HD_DIOR_L

5

HD_DMACK_L

LVDS_L2

10 MIL SPACING

LVDS_L2P

LVDS_L2

10 MIL SPACING

CLKLVDS_UN

CLKLVDS_U

10 MIL SPACING

4

19 22 39

13 24

CLKLVDS_UP

CLKLVDS_U

10 MIL SPACING

4

19 22 39

13

LVDS_U0N

LVDS_U0

10 MIL SPACING

19 22 39

13 24

LVDS_U0P

LVDS_U0

10 MIL SPACING

19 22 39

13

LVDS_U1N

LVDS_U1

10 MIL SPACING

19 22 39 19 22 39

19 22 39 19 22 39

200

100 MHZ

24

LVDS_U1P

LVDS_U1

10 MIL SPACING

200

100 MHZ

24

LVDS_U2N

LVDS_U2

10 MIL SPACING

200.0000

24

LVDS_U2P

LVDS_U2

10 MIL SPACING

200.0000

24

TMDS_CONN_CLKN

CLKCONN_TMDS

10 MIL SPACING

4

22 39

200.0000

24

TMDS_CONN_CLKP

CLKCONN_TMDS

10 MIL SPACING

4

22 39

5

200.0000

24

TMDS_CLKN

CLKTMDS

10 MIL SPACING

4

20 22

HD_CS0_L

5

200.0000

24

TMDS_CLKP

CLKTMDS

10 MIL SPACING

4

HD_CS1_L

5

200.0000

24

TMDS_DN<0>

TMDS_D0

10 MIL SPACING

200.0000

13 24

TMDS_DP<0>

TMDS_D0

10 MIL SPACING

20 22 39

200.0000

24

TMDS_DN<1>

TMDS_D1

10 MIL SPACING

20 22 39

13 24

TMDS_DP<1>

TMDS_D1

10 MIL SPACING

20 22 39

TMDS_DN<2>

TMDS_D2

10 MIL SPACING

20 22 39

TMDS_DP<2>

TMDS_D2

10 MIL SPACING

20 22 39

TOTAL UIDE+HD SKEW <500MIL

10 MIL SPACING

HD_DMARQ HD_IOCHRDY

5

HD_INTRQ

5

10 MIL SPACING

EIDE_DATA<15..0>

33 MHZ

EIDE_ADDR<2..0>

33 MHZ

13 24 13 24

EIDE_CS0_L

13 24

EIDE_CS1_L

13 24

EIDE_RD_L

13 24

EIDE_IOCHRDY

13 24

EIDE_INT

13 24

EIDE_RST_L

13 24

EIDE_DMACK_L

13 24

EIDE_DMARQ

13 24

EIDE_OPTICAL_DATA<15..0>

33 MHZ

EIDE_OPTICAL_ADDR<2..0>

33 MHZ

24 39 24 39

EIDE_OPTICAL_CS0_L

24 39

EIDE_OPTICAL_CS1_L

24 39

EIDE_OPTICAL_RD_L

24 39

EIDE_OPTICAL_WR_L

24 39

EIDE_OPTICAL_IOCHRDY

24 39

EIDE_OPTICAL_INT

24 39

EIDE_OPTICAL_RST_L

24 39

EIDE_OPTICAL_DMAACK_L

24 39

EIDE_OPTICAL_DMA_RQ

24 39

ENET_LINK_RXD<7..0>

5

13 27

ENET_RX_DV

13 27

ENET_RX_ER

13 27

ENET_PHY_TXD<7..0>

5

POWER SUPPLIES

13 27

ENET_LINK_TXD<7..0>

13

ENET_PHY_TX_ER

5

13 27

ENET_LINK_TX_ER

13

ENET_PHY_TX_EN

5

13 27

ENET_LINK_TX_EN

13

ENET_MDIO

13 27

ENET_MDC

13 27

ENET_COL

13 27

ENET_CRS

13 27

FW_PHY_DATA<7..0>

USB

13 24

EIDE_WR_L

FW_LINK_DATA<7..0>

TMDS

THERMOSTAT

26

MIN_LINE_WIDTH=5

10 MIL SPACING

26

NEC_USB_DAP

NEC_USB_DA

USB_DEM

USB_DE

5 MIL SPACING

14

USB_DEP

USB_DE

5 MIL SPACING

14

NEC_USB_DBM

NEC_USB_DB

MIN_LINE_WIDTH=5

10 MIL SPACING

26

MIN_LINE_WIDTH=5

10 MIL SPACING

26

USB_DF

5 MIL SPACING

14

USB_DFP

USB_DF

5 MIL SPACING

14

BT_USB_DM

BT_USB_D

5 MIL SPACING

14 24 39

BT_USB_DP

BT_USB_D

5 MIL SPACING

14 24 39

NEC_USB_RSDM1

NEC_USB_RSD1

MIN_LINE_WIDTH=5

10 MIL SPACING

26

NEC_USB_RSDP1

NEC_USB_RSD1

MIN_LINE_WIDTH=5

10 MIL SPACING

26

NEC_USB_RSDM2

NEC_USB_RSD2

MIN_LINE_WIDTH=5

10 MIL SPACING

26

MIN_LINE_WIDTH=5

NEC_USB_RSDP2

NEC_USB_RSD2

10 MIL SPACING

26

MODEM_USB_DM

MODEM_USB_D

5 MIL SPACING

14 25 39

MODEM_USB_DP

MODEM_USB_D

5 MIL SPACING

14 25 39

LEFT_USB_DM

LEFT_USB

MIN_LINE_WIDTH=5

10 MIL SPACING

24 26 39

LEFT_USB_DP

LEFT_USB

MIN_LINE_WIDTH=5

10 MIL SPACING

24 26 39

RIGHT_USB_DM

RIGHT_USB

MIN_LINE_WIDTH=5

10 MIL SPACING

26 32 39

RIGHT_USB_DP

RIGHT_USB

MIN_LINE_WIDTH=5

10 MIL SPACING

1772_CSS

1772_CSSP

1772_CSS

1772_CSIN

1772_CSI

1772_CSIP

1772_CSI

3V_SNSM

3V_SNS

3V_SNSP

3V_SNS

5V_SNSM

5V_SNS

5V_SNSP

5V_SNS

THERM1_DM

THERM1

THERM1_DP

THERM1

THERM2_DM

THERM2

THERM2_DP

THERM2

THERM1_M_DM

THERM1_MAIN

THERM1_M_DP

THERM1_MAIN

5

13 28

THERM2_M_DM

THERM2_MAIN

5

28

THERM2_M_DP

THERM2_MAIN

FW_LINK_CNTL<1..0>

13 28

THERM1_A_DM

THERM1_ALT

FW_PHY_CNTL<1..0>

28

THERM1_A_DP

THERM1_ALT

FW_LINK_LREQ

13

THERM2_A_DM

THERM2_ALT

FW_PHY_LREQ

13 28

THERM2_A_DP

THERM2_ALT

FW_PINT

DIFF DIFF DIFF DIFF DIFF DIFF DIFF DIFF DIFF DIFF DIFF DIFF DIFF DIFF DIFF DIFF DIFF DIFF DIFF DIFF

T = 0.7MIL (TRACE THICKNESS) S = 10MIL (SEPERATION OF DIFF TRACES) ZSINGLE = 53.37OHM ZDIFF = 107.17OHM

ER = 4.3 (DIELECTRIC CONSTANT) W = 4MIL(USB 1.1)/ 5MIL(USB 2.0) (TRACE WIDTH) B = 12.2MIL (DIST BETW 2 GND PLANES) T = 0.7MIL (TRACE THICKNESS) S = 5MIL (USB 1.1) (SEPERATION OF DIFF TRACES) S = 10MIL (USB 2.0) (SEPERATION OF DIFF TRACES) ZSINGLE = 51.5OHM (USB 1.1)/ 46.2OHM (USB 2.0) ZDIFF = 89.3OHM (USB 1.1)/ 89.4OHM (USB 2.0)

26 32 39

31 31 31 31 33 33 33 33

SIGNAL CONSTRAINTS - PAGE 2

25 25


25 25

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

25

SIZE

25 25 25

APPLE COMPUTER INC.

D

DRAWING NUMBER

6

5

4

3

2

REV.

051-6598

SCALE

13 28

7

B

INTERNAL LAYER (USB1.1/USB 2.0)

SHT NONE

8

C

20 22

10 MIL SPACING

1772_CSSN

ER = 4.3 (DIELECTRIC CONSTANT) W = 3.4MIL (TRACE WIDTH) B = 12.2MIL (DIST BETW 2 GND PLANES)

20 22 39

MIN_LINE_WIDTH=5

NEC_USB_DB

FOR FIREWIRE

19 22 39

NEC_USB_DA

NEC_USB_DBP

T = 0.7MIL (TRACE THICKNESS) S = 10MIL (SEPERATION OF DIFF TRACES) ZSINGLE = 51.57OHM ZDIFF = 99.8OHM

19 22 39

NEC_USB_DAM

USB_DFM

ER = 4.3 (DIELECTRIC CONSTANT) W = 4MIL (TRACE WIDTH) B = 12.2MIL (DIST BETW 2 GND PLANES)

29 39

CLKLVDS_LN

200

UPPER

INTERNAL LAYER

29 39

UIDE_ADDR<2..0>

10 MIL SPACING

D

29 39

UIDE_DATA<6..0>

UIDE_IOCHRDY

FIREWIRE MII

SPACING DELETED BECAUSE

33 MHz

UIDE_CS1_L

A

ENET_MDI1

MIN_DAISY_CHAIN

UIDE_DMARQ

ETHERNET MII

ENET_MDI0

MDI_M<1>

PCI_CBE<3..0>

UIDE_RST_L

OPTICAL

MDI_P<0>

FW_TPO0P

UIDE_DATA<15..8>

NET_SPACING_TYPE MAX_VIAS

ENET_MDI0

9 12 17 24 26 39

UIDE_DIOR_L

B

MAX_EXPOSED_LENGTH

MDI_M<0>

33 MHz

UIDE_DIOW_L

INTREPID

DIFFERENTIAL_PAIR

MIN_DAISY_CHAIN

UIDE_DATA<7>

EIDE

FIREWIRE

SIG_NAME

PCI_AD<31..0>

PCI_PAR

C

12 18

250.0000

GPU_DVOD<0..11>

ULTRA ATA-100

12 18

100

100

ETHERNET

12 18

AGP_REQ_L

AGP_RBF_L

PCI

66 MHz

250.0000

AGP_IRDY_L

DVO

100

1

Differential Signals

PULSE_PARAM

5

AGP_CBE<3..2>

AGP CONTROL

NO_TEST

AGP_AD<15..0>

AGP_AD_STB<1>

AGP SIDEBAND

NET_SPACING_TYPE

2

3

4

5

OF

01

37 44 1

A

8

6

7

POWER NET CONSTRAINTS GROUP

SIG_NAME

VOLTAGE

MIN_LINE_WIDTH

GROUP

SIG_NAME U_VCORE_SLEEP

U

MIN_NECK_WIDTH

U_AVDD MAXBUS_SLEEP

MAIN/SLEEP

+24V_PBUS

VOLTAGE=24V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

+BATT

VOLTAGE=12.6V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

+PBUS

VOLTAGE=12.8V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

+5V_MAIN

D

ADAPTER

BATTERY CHARGER

VOLTAGE=5V

MIN_LINE_WIDTH=25

39

39

DDR RAM INTREPID PLLS

MIN_NECK_WIDTH=10

+5V_SLEEP

VOLTAGE=5V

MIN_LINE_WIDTH=25

+3V_MAIN

VOLTAGE=3.3V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

+3V_SLEEP

VOLTAGE=3.3V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=6

MIN_NECK_WIDTH=10

+3V_PMU

VOLTAGE=3.3V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

+2_5V_MAIN

VOLTAGE=2.5V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

+2_5V_SLEEP

VOLTAGE=2.5V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

+1_8V_MAIN

VOLTAGE=1.8V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=6

+1_8V_SLEEP

VOLTAGE=1.8V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

+1_5V_MAIN

VOLTAGE=1.5V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

+1_5V_SLEEP

VOLTAGE=1.5V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

+1_5V_LDO

VOLTAGE=1.5V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

39

REFERENCE 35

+1_5V_SLEEP_VIN

VOLTAGE=1.5V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

35

+ADAPTER

VOLTAGE=24V

MIN_LINE_WIDTH=50

MIN_NECK_WIDTH=10

31 32

+ADAPTER_SW

VOLTAGE=24V

MIN_LINE_WIDTH=50

MIN_NECK_WIDTH=10

31

+ADAPTER_SENSE

VOLTAGE=24V

MIN_LINE_WIDTH=50

MIN_NECK_WIDTH=10

31

+BATT_POS

VOLTAGE=16.8V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

31 39

BATT_NEG

VOLTAGE=0V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

31 39

1772_DCIN

VOLTAGE=24V

MIN_LINE_WIDTH=10

1772_LX

VOLTAGE=12.6V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

31

+BATT_14V_FUSE

VOLTAGE=12.6V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

31

+BATT_24V_FUSE

VOLTAGE=12.6V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

31

+BATT_RSNS

VOLTAGE=12.6V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

31

+BATT_VSNS

VOLTAGE=12.6V

MIN_LINE_WIDTH=10

MIN_NECK_WIDTH=10

31

1772_LDO

VOLTAGE=5.4V

MIN_LINE_WIDTH=10

31

1772_DLOV

VOLTAGE=5.4V

MIN_LINE_WIDTH=10

31

1772_GND

VOLTAGE=0V

MIN_LINE_WIDTH=10

31

CARDBUS ATI M10

31

I331

PMU

32

I332

+ADAPTER_OR_BATT

VOLTAGE=24V

MIN_LINE_WIDTH=10

32

MIN_NECK_WIDTH=10

9 10 15 16

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

14

+1_5V_INTREPID_PLL

VOLTAGE=1.5V

MIN_LINE_WIDTH=15

MIN_NECK_WIDTH=10

8 12 14

+1_5V_INTREPID_PLL1

VOLTAGE=1.5V

MIN_LINE_WIDTH=15

MIN_NECK_WIDTH=6

14

LTC3707

+1_5V_INTREPID_PLL2

VOLTAGE=1.5V

MIN_LINE_WIDTH=15

MIN_NECK_WIDTH=6

14

5V SWITCHER

+1_5V_INTREPID_PLL3

VOLTAGE=1.5V

MIN_LINE_WIDTH=15

MIN_NECK_WIDTH=6

14

+1_5V_INTREPID_PLL4

VOLTAGE=1.5V

MIN_LINE_WIDTH=15

MIN_NECK_WIDTH=5

14

+3V_PMU_AVCC

VOLTAGE=3.3V

MIN_LINE_WIDTH=10

MISC HD

+5V_HD_SLEEP +HD_LOGIC_SLEEP

VOLTAGE=5V VOLTAGE=3.3V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

TRACKPAD

HALL EFFECT VIDEO

+5V_TPAD_SLEEP

+3V_HALL_EFFECT

SOUND

MIN_LINE_WIDTH=10

23 39

2_5V_LX

9

VOLTAGE=2.5V

MIN_LINE_WIDTH=50

MIN_NECK_WIDTH=10

35

MIN_LINE_WIDTH=10

12 18

2_5V_BST

VOLTAGE=5V

MIN_LINE_WIDTH=15

MIN_NECK_WIDTH=10

35

MIN_LINE_WIDTH=10

9

2_5V_BOOST

VOLTAGE=5V

MIN_LINE_WIDTH=15

MIN_NECK_WIDTH=10

35

UIDE_REF

VOLTAGE=0V

2_5V_DH

VOLTAGE=2.5V

MIN_LINE_WIDTH=20

MIN_NECK_WIDTH=10

35

VOLTAGE=3.3V

MIN_LINE_WIDTH=8 MIN_NECK_WIDTH REDUCED FOR TESTPOINTS MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10

13

+VCC_CBUS_SW

2_5V_DL

VOLTAGE=2.5V

MIN_LINE_WIDTH=20

MIN_NECK_WIDTH=10

35

+VPP_CBUS_SW

VOLTAGE=5V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

17

GPU_VCORE

VOLTAGE=1.2V

MIN_LINE_WIDTH=30

MIN_NECK_WIDTH=10

18 19 39

1_5V_FB

+GPU_MEM

VOLTAGE=1.5V

MIN_LINE_WIDTH=8

VOLTAGE=2.5V

MIN_LINE_WIDTH=30

MIN_NECK_WIDTH=10

18 21

1_5V_LX

+3V_GPU

VOLTAGE=1.5V

MIN_LINE_WIDTH=50

MIN_NECK_WIDTH=10

35

VOLTAGE=3.3V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

12 18 19 21

1_5V_BST

VOLTAGE=5V

MIN_LINE_WIDTH=15

MIN_NECK_WIDTH=10

35

1_5V_BOOST

VOLTAGE=5V

MIN_LINE_WIDTH=15

MIN_NECK_WIDTH=10

35

1_5V_DH

VOLTAGE=1.5V

MIN_LINE_WIDTH=20

MIN_NECK_WIDTH=10

35

1_5V_DL

VOLTAGE=1.5V

MIN_LINE_WIDTH=20

MIN_NECK_WIDTH=10

35

VOLTAGE=3.3V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=8

21

+1_5V_AGP

VOLTAGE=1.5V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

12 15 16 18 19 21

GPU_MEM_IO

VOLTAGE=2.5V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

VOLTAGE=2.5V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

18 19 20 21

+2_5V_GPU_PNLIO

VOLTAGE=2.5V

MIN_LINE_WIDTH=20

MIN_NECK_WIDTH=10

21

MIN_LINE_WIDTH=20

MIN_NECK_WIDTH=10

21

+1_5V_GPU_VDD15

VOLTAGE=1.5V

MIN_LINE_WIDTH=20

19

VOLTAGE=1.8V VOLTAGE=1.8V VOLTAGE=1.2V

MIN_LINE_WIDTH=15 MIN_LINE_WIDTH=15

MIN_NECK_WIDTH=10 MIN_NECK_WIDTH=10 MIN_NECK_WIDTH=10

LVDS

MIN_LINE_WIDTH=10

I345

+1_5V_AGP_NECK

MIN_LINE_WIDTH=10

+1_8V_PVDD_NECK

VOLTAGE=2.5V

MIN_LINE_WIDTH=10

I346 I344

GPU_VCORE_NECK

ENET_CTAP_CHGND

MIN_LINE_WIDTH=15

MIN_NECK_WIDTH=10

MIN_LINE_WIDTH=15

MIN_NECK_WIDTH=10

VOLTAGE=2.5V


MIN_NECK_WIDTH=10

VOLTAGE=1.8V

MIN_LINE_WIDTH=10

MIN_NECK_WIDTH=10 MIN_NECK_WIDTH=10

VOLTAGE=1.8V

MIN_LINE_WIDTH=10

VOLTAGE=5V

MIN_LINE_WIDTH=15

MIN_NECK_WIDTH=10

22 39

+1_5V_SLEEP_NECK +2_5V_GPU

VOLTAGE=1.5V

MIN_LINE_WIDTH=10

I350 I352

VOLTAGE=2.5V

MIN_LINE_WIDTH=10

GPU_TV_GND2

VOLTAGE=0V

MIN_LINE_WIDTH=25

22

VOLTAGE=0V

MIN_LINE_WIDTH=25

22 39

VOLTAGE=0V

MIN_LINE_WIDTH=25

I355 I354

MIN_NECK_WIDTH=10

VOLTAGE=0V

MIN_LINE_WIDTH=10

23 39

KBD_LED2_OUT

VOLTAGE=0V

MIN_LINE_WIDTH=10

23 39

1_5V_ILIM

MIN_LINE_WIDTH=8

35

2_5V_ILIM

MIN_LINE_WIDTH=8

35

MAX1715_TON

MIN_LINE_WIDTH=8

35

MAX1715_SKIP

MIN_LINE_WIDTH=8

35

MAX1715_REF

VOLTAGE=2.0V

MIN_LINE_WIDTH=8

MAX1715_VCC

VOLTAGE=5V

MIN_LINE_WIDTH=20

MIN_NECK_WIDTH=10

35

MAX1715_GND

VOLTAGE=0V

MIN_LINE_WIDTH=30

MIN_NECK_WIDTH=10

35

C

18

MAX1717

VCORE_VCC

VOLTAGE=5V

MIN_LINE_WIDTH=20

MIN_NECK_WIDTH=10

34

21

VCORE_LX

VOLTAGE=1.4V

MIN_LINE_WIDTH=200

MIN_NECK_WIDTH=10

34

21

VCORE_DH

MIN_LINE_WIDTH=20

MIN_NECK_WIDTH=10

34

21

VCORE_DL

MIN_LINE_WIDTH=20

MIN_NECK_WIDTH=10

34

21

VCORE_BOOST

VOLTAGE=5V

MIN_LINE_WIDTH=15

MIN_NECK_WIDTH=10

34

21

VCORE_BST

VOLTAGE=5V

MIN_LINE_WIDTH=15

MIN_NECK_WIDTH=10

34

21

VCORE_ILIM

MIN_LINE_WIDTH=8

34

18

VCORE_REF

MIN_LINE_WIDTH=8

34

18

VCORE_TON

MIN_LINE_WIDTH=8

34

19

VCORE_CC

MIN_LINE_WIDTH=8

34

MIN_LINE_WIDTH=8

34 39

MIN_LINE_WIDTH=8

34

21

VCORE_FB

21

VOLTAGE=5V

VOLTAGE=1.4V

VCORE_TIME

19

VCORE_VGATE

MIN_LINE_WIDTH=8

14 34

VCORE_GND

VOLTAGE=0V

MIN_LINE_WIDTH=30

34

VCORE_GNDSNS

VOLTAGE=0V

MIN_LINE_WIDTH=8

34

VCORE_SNS

VOLTAGE=1.4V

MIN_LINE_WIDTH=8

34

VCORE_GNDDIV

VOLTAGE=0V

MIN_LINE_WIDTH=8

1778_VIN

VOLTAGE=14V

MIN_LINE_WIDTH=20

MIN_NECK_WIDTH=10

19

1778_VCC

VOLTAGE=5V

MIN_LINE_WIDTH=20

MIN_NECK_WIDTH=10

19

1778_GND

VOLTAGE=0V

MIN_LINE_WIDTH=30

MIN_NECK_WIDTH=10

19

20

1778_BST

VOLTAGE=5V

MIN_LINE_WIDTH=15

MIN_NECK_WIDTH=10

19

20

1778_BST_RC

VOLTAGE=5V

MIN_LINE_WIDTH=15

MIN_NECK_WIDTH=10

19

20

1778_TG

MIN_LINE_WIDTH=20

MIN_NECK_WIDTH=10

19

1778_BG

MIN_LINE_WIDTH=20

MIN_NECK_WIDTH=10

19

MIN_LINE_WIDTH=50

MIN_NECK_WIDTH=10

19 19 19 21

34

21 21

MIN_NECK_WIDTH=10

+3V_SI_PLLVCC

VOLTAGE=3.3V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=8

+3V_SI_AVCC +3V_SI_VCC

VOLTAGE=3.3V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=8

VOLTAGE=3.3V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=8

21

LTC1778

GPU_VCORE_SW

88E1111

35

21

22 39

KBD_LED1_OUT

35

21

19

MIN_LINE_WIDTH=10

+5V_DDC_SLEEP

22

MIN_NECK_WIDTH=10

VOLTAGE=1.8V

MIN_LINE_WIDTH=10

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10 MIN_NECK_WIDTH=10

VOLTAGE=1.8V

VOLTAGE=3.3V

VOLTAGE=0V

MIN_NECK_WIDTH=10

VOLTAGE=1.8V

+1_8V_SLEEP_NECK

VOLTAGE=1.2V

MIN_LINE_WIDTH=8

19

1778_ITH

MIN_LINE_WIDTH=8

19

1778_ITH_RC

MIN_LINE_WIDTH=8

19

+2_5V_MARVELL

VOLTAGE=2.5V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

27

1_5V_2_5V_OK

MIN_LINE_WIDTH=8

35

VOLTAGE=0V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

25 39

+2_5V_MARVELL_AVDD

VOLTAGE=2.5V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=8

27

1778_VFB

FANR_GND

MIN_LINE_WIDTH=8

19 39

VOLTAGE=0V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

25 39

+1_0V_MARVELL

VOLTAGE=1.0V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=8

27

1778_FCB

MIN_LINE_WIDTH=8

19

LTC3405_SW

VOLTAGE=1.0V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=8

27

1778_VRNG

MIN_LINE_WIDTH=8

19

LM2594_IN

VOLTAGE=3.3V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

28

+3V_FW_ESD_ILIM

VOLTAGE=3.3V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

29

+3V_FW_ESD

VOLTAGE=3.3V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

29

+FW_FUSE

VOLTAGE=12.8V

MIN_LINE_WIDTH=100

MIN_NECK_WIDTH=12

29

+FW_SW

VOLTAGE=12.8V

MIN_LINE_WIDTH=100

MIN_NECK_WIDTH=12

29

1_8V_VFB

MIN_LINE_WIDTH=8

+FW_PWR_OR

VOLTAGE=33V

MIN_LINE_WIDTH=100

MIN_NECK_WIDTH=12

28 29

LTC3411_ITH_RC

MIN_LINE_WIDTH=8

+FW_VP0

VOLTAGE=33V

MIN_LINE_WIDTH=100

MIN_NECK_WIDTH=12

29

LTC3411_ITH

MIN_LINE_WIDTH=8

+FW_PWR_PORTA

VOLTAGE=33V

MIN_LINE_WIDTH=100

MIN_NECK_WIDTH=12

29

LTC3411_SYNC

MIN_LINE_WIDTH=8

+FW_VP1

VOLTAGE=33V

MIN_LINE_WIDTH=100

MIN_NECK_WIDTH=12

29

LTC3411_SHDN

MIN_LINE_WIDTH=8

+3V_FW

VOLTAGE=3.3V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

28 29

+3V_FW_UF

VOLTAGE=3.3V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

28

LTC1962_INT_VIN

+3V_FW_AVDD_PORT2

VOLTAGE=3.3V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

28

+3V_FW_AVDD_PORT1

VOLTAGE=3.3V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=6

28

+3V_FW_AVDD_PORT0

VOLTAGE=3.3V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

+3V_FW_AVDD

VOLTAGE=3.3V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

+1_95V_FW_DVDD

VOLTAGE=1.95V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

28

+1_95V_FW_DVDD_RX0

VOLTAGE=1.95V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

28

+1_95V_FW_DVDD_TX0

VOLTAGE=1.95V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

28

+1_95V_FW_DVDD_PORT1

VOLTAGE=1.95V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

28

+1_95V_FW_PLLVDD

VOLTAGE=1.95V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

28

+1_95V_FW_PLL400VDD

VOLTAGE=1.95V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

28

+1_95V_FW_PLL500VDD

VOLTAGE=1.95V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

28

FW_VGND0

VOLTAGE=0V

MIN_LINE_WIDTH=100

MIN_NECK_WIDTH=12

29

FW_VGND1

VOLTAGE=0V

MIN_LINE_WIDTH=100

MIN_NECK_WIDTH=12

29

FW_TPO0R

VOLTAGE=0V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

29 39

NEC_AVDD

VOLTAGE=3.3V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

26

+3V_NEC_VDD

VOLTAGE=3.3V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

26

+3V_CG_PLL_MAIN

VOLTAGE=3.3V

MIN_LINE_WIDTH=15

MIN_NECK_WIDTH=8

14

+2_5V_CG_MAIN

VOLTAGE=2.5V

MIN_LINE_WIDTH=15

MIN_NECK_WIDTH=8

14

+5V_SOUND_SLEEP

VOLTAGE=5V VOLTAGE=0V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=15

25

VOLTAGE=0V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=6

GND

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=12

CHGND1

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=12

CHGND2

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=12

CHGND3

CHGND1 VOLTAGE=0V CHGND2 VOLTAGE=0V CHGND3 MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=12

CHGND4

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=12

CHGND5

39

CHGND4

CHGND5 MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=12

CHGND6

CHGND6

VOLTAGE=0V

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=12

27

USB 2.0 INTREPID SSCG

LTC3411_VCC

VOLTAGE=3.3V

MIN_LINE_WIDTH=20

MIN_NECK_WIDTH=10

LTC3411_GND

VOLTAGE=0V

MIN_LINE_WIDTH=30

MIN_NECK_WIDTH=10

1_8V_SW

VOLTAGE=1.8V

MIN_LINE_WIDTH=30

MIN_NECK_WIDTH=10

35

MIN_LINE_WIDTH=20

MIN_NECK_WIDTH=10

14

LTC1962_L3_VIN

MIN_LINE_WIDTH=20

MIN_NECK_WIDTH=10

LTC1962_L3_VOUT

MIN_LINE_WIDTH=20

MIN_NECK_WIDTH=10

28

LTC1962_1V5_VIN

MIN_LINE_WIDTH=20

MIN_NECK_WIDTH=10

28

LTC1962_1V5_VOUT

MIN_LINE_WIDTH=20

MIN_NECK_WIDTH=10

LTC3411

LTC1962 INT PLLS

SIGNAL CONSTRAINTS - PAGE 3 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

D

DRAWING NUMBER

SHT NONE

7

6

5

4

3

2

REV.

051-6598

SCALE

8

B

19

1778_ION

FANL_GND

VOLTAGE=0V

I/O AREA

MIN_LINE_WIDTH=15 MIN_LINE_WIDTH=15 MIN_LINE_WIDTH=15

I349

VOLTAGE=0V

I/O AREA

GPU_VCORE_VDDCI

22 39

VOLTAGE=0V

A

+1_8V_GPU_VDDDI

CONTROL

19 21

VOLTAGE=1.5V

MIN_NECK_WIDTH=10

GPU_TV_GND1

MIN_NECK_WIDTH=10

+1_5V_AGP_GPU

MIN_LINE_WIDTH=25

VOLTAGE=0V

TRACKPAD

MIN_LINE_WIDTH=20

VOLTAGE=5V

FW

INVERTER

VOLTAGE=1.8V

VOLTAGE=1.8V

I353

21

VOLTAGE=1.8V

+5V_INV_SW

SILICON IMIAGE

MIN_NECK_WIDTH=10

1.5V SWITCHER

21

+1_8V_GPU

MIN_LINE_WIDTH=10

SND_AGND

I/O AREA

MIN_LINE_WIDTH=25

VOLTAGE=3.3V

22

17

+3V_GPU_FLT

VOLTAGE=2.5V

2.5V SWITCHER

D

33

MIN_LINE_WIDTH=10

+2_5V_SLEEP_NECK2

MIN_NECK_WIDTH=10

33

VOLTAGE=0V

I351

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

VOLTAGE=1.25V

22

VOLTAGE=3.3V

33

VOLTAGE=1.25V

MIN_NECK_WIDTH=10

22

MIN_NECK_WIDTH=10

INT_MEM_REF_H

MIN_LINE_WIDTH=25

22

MIN_LINE_WIDTH=25

INT_AGP_VREF

VOLTAGE=5V

MIN_NECK_WIDTH=10

VOLTAGE=3.3V

32

INT_MEM_VREF

+5V_INV_UF_SW

MIN_NECK_WIDTH=10

33

3V_SW

14

MIN_LINE_WIDTH=10

MIN_LINE_WIDTH=12

33

MIN_NECK_WIDTH=10

MIN_NECK_WIDTH=6

VOLTAGE=1.8V

MIN_LINE_WIDTH=15

33

MIN_NECK_WIDTH=10

MIN_LINE_WIDTH=25

MIN_LINE_WIDTH=15

+GPU_VDD15_NECK

VOLTAGE=3.3V

MIN_NECK_WIDTH=10

MIN_LINE_WIDTH=25

VOLTAGE=5V

VOLTAGE=1.5V

I348

VOLTAGE=5V

MIN_LINE_WIDTH=10

VOLTAGE=5V

5V_RSNS

+1_5V_INTREPID_PLL8

22 39

+3V_LCD

VOLTAGE=5V

5V_SW

MIN_LINE_WIDTH=10

MIN_NECK_WIDTH=10

+5V_DDC_SLEEP_UF

3707_INTVCC

MIN_LINE_WIDTH=25

MIN_LINE_WIDTH=25

TV_GND2

FAN GND

23 39

31 32

VOLTAGE=0V

VOLTAGE=12.8V

TV_GND1

KB LED

VOLTAGE=3.3V

MIN_LINE_WIDTH=10

MIN_NECK_WIDTH=10

VOLTAGE=3.3V

+12_8V_INV

+3V_LCD_SW

B

VOLTAGE=5V


3707_SGND

VOLTAGE=1.8V

I342

VOLTAGE=0V VOLTAGE=1.2V

3V_RSNS

+3V_SLEEP_NECK

24

32

1V20_REF

8

MAX1715

32

MIN_NECK_WIDTH=10

1625_SGND

12

I347

24 33

32

MIN_NECK_WIDTH=6

I343

I338

25 30

MIN_LINE_WIDTH=10

MIN_NECK_WIDTH=6


I337

VOLTAGE=5V

MIN_LINE_WIDTH=15

VOLTAGE=1.5V VOLTAGE=1.8V

32

1625_INTVCC

MIN_LINE_WIDTH=15

+GPU_VDD15_UF +2_5V_SLEEP_NECK1

MIN_LINE_WIDTH=10

32

VOLTAGE=1.5V

I339

VOLTAGE=3.3V

MIN_LINE_WIDTH=10

VOLTAGE=1.5V

MIN_LINE_WIDTH=10

+3V_PMU_ESR

MIN_LINE_WIDTH=25

VOLTAGE=5V

+1_5V_INTREPID_PLL7

VOLTAGE=3.3V

I335

VOLTAGE=12.8V

1625_EXTVCC

+1_5V_INTREPID_PLL6

+3V_ATI_SS

I333

32

MIN_NECK_WIDTH

MIN_LINE_WIDTH=10

12

VOLTAGE=3.3V

32 33

MIN_LINE_WIDTH=10

MIN_LINE_WIDTH

VOLTAGE=24V

1625_VSW

MIN_NECK_WIDTH=5

+3V_ATI_OSC_SLEEP

30 32

MIN_LINE_WIDTH=10

VOLTAGE=4.85V

3V SWITCHER

VOLTAGE

1625_VIN

MIN_LINE_WIDTH=15

I340

MIN_LINE_WIDTH=10

VOLTAGE=4.6V

+4_85V_ESR

11

SIG_NAME

1

VOLTAGE=1.5V

I341

VOLTAGE=4.85V

+4_6V_BU

5 7 8 15 16 23 34

MIN_LINE_WIDTH=25

MIN_LINE_WIDTH=10

VOLTAGE=2.5V VOLTAGE=1.8V

+4_85V_RAW

14V SWITCHER

VOLTAGE=3.3V

+2_5V_GPU_A2VDD +1_8V_GPU_AVDD +1_8V_GPU_PNLPLL +1_8V_GPU_PNLIO +GPU_MCLK +1_8V_GPU_AVDDQ +1_8V_GPU_MEMPLL

I336 I334

MIN_NECK_WIDTH=10

5

VOLTAGE=2.5V

+1_8V_ATI_PVDD

MIN_LINE_WIDTH=10

MIN_LINE_WIDTH=25

MIN_NECK_WIDTH=10

LTC1625

VOLTAGE=1.25V

+GPU_MEMCORE

VOLTAGE=24V

VOLTAGE=1.8V

MIN_LINE_WIDTH=25

GROUP 5 6 34 39

+3V_INTREPID_USB

GPU_MEM_IO_FLT

+ADAPTER_ILIM

VOLTAGE=1.4V

MIN_NECK_WIDTH MIN_NECK_WIDTH=10

+2_5V_INTREPID

+1_8V_GPU_PLL

C

MIN_LINE_WIDTH MIN_LINE_WIDTH=25

DDR_VREF

+1_5V_INTREPID_PLL5 39

VOLTAGE VOLTAGE=1.4V

2

3

4

5

OF

01

38 44 1

A

8

6

7

2

3

4

5

1

FUNCTIONAL TEST POINTS FUNC_TEST=YES

FUNC_TEST=YES JTAG_ASIC_TMS

FUNC_TEST=YES JTAG_ASIC_TDI

D

FUNC_TEST=YES JTAG_ASIC_TDO

13 27

27

13 14

TMDS_CONN_CLKP

FUNC_TEST=YES

22 37

FUNC_TEST=YES VGA_R 22

FUNC_TEST=YES VGA_G

TV_C

22

FUNC_TEST=YES TV_Y

22

FUNC_TEST=YES TV_COMP

22

9 12 17 24 26 37

FUNC_TEST=YES PCI_PAR

12 17 24 26 37

FUNC_TEST=YES PCI_AD<8>

9 12 17 24 26 37

FUNC_TEST=YES PCI_CBE<0>

12 17 24 26 37


22

EIDE_OPTICAL_CS0_L

PCI_CBE<1>

FUNC_TEST=YES 24 37

23 30

FUNC_TEST=YES KBD_Y<0>

23 30

+5V_INV_SW

FUNC_TEST=YES

KBD_Y<1>

24 37

22 38

FUNC_TEST=YES LEFT_USB_DM

FUNC_TEST=YES

FUNC_TEST=YES EIDE_OPTICAL_RST_L

12 17 24 26 37

KBD_X<9>

24 37

EIDE_OPTICAL_CS1_L

FUNC_TEST=YES 9 12 17 24 26 37

FUNC_TEST=YES

FUNC_TEST=YES

FUNC_TEST=YES


FW_TPO1P

23 30

24 26 37

FUNC_TEST=YES LEFT_USB_DP

29 37

24 26 37

D

FUNC_TEST=YES FUNC_TEST=YES

FUNC_TEST=YES JTAG_ASIC_TCK

13 27

VGA_B

FUNC_TEST=YES

FUNC_TEST=YES SND_TO_AUDIO

22

14 25

FUNC_TEST=YES

FUNC_TEST=YES

PCI_AD<10>

9 12 17 24 26 37


9 12 17 24 26 37

PCI_CBE<2>

EIDE_OPTICAL_WR_L

12 17 24 26 37


24 37

FUNC_TEST=YES FW_TPO1N

23 30

RIGHT_USB_DM

29 37

26 32 37

FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES JTAG_ASIC_TRST_L

FUNC_TEST=YES

FUNC_TEST=YES 13 27

VGA_VSYNC

SND_SYNC

22

14 25

FUNC_TEST=YES EIDE_OPTICAL_IOCHRDY

FUNC_TEST=YES PCI_CBE<3>

12 17 24 26 37

FUNC_TEST=YES

KBD_Y<3>

24 37

FW_TPI1P

23 30

RIGHT_USB_DP

29 37

26 32 37

FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES U_CHKSTP_OUT_L

FUNC_TEST=YES 5

VGA_HSYNC

5

DVI_DDC_CLK_UF

FUNC_TEST=YES U_SRESET_L

FUNC_TEST=YES SND_CLKOUT

22

14 25 36

FUNC_TEST=YES 22

FUNC_TEST=YES

FUNC_TEST=YES


9 12 17 24 26 37

AIRPORT_PCI_REQ_L


9 12 17 24 26 37

AIRPORT_PCI_GNT_L

EIDE_OPTICAL_INT

12 24

TPAD_F_TXD

12 24

FW_TPI1N

23 30

KBD_Y<5>

23

NEC_LEFT_USB_PWREN

29 37

FUNC_TEST=YES

FUNC_TEST=YES

FUNC_TEST=YES

FUNC_TEST=YES

FUNC_TEST=YES

KBD_Y<4>

24 37

CHARGE_LED_L

23 30

24 26

FUNC_TEST=YES NEC_LEFT_USB_OVERCURRENT

30 31

24 26

FUNC_TEST=YES FUNC_TEST=YES U_HRESET_L

FUNC_TEST=YES

FUNC_TEST=YES 5 7 23

DVI_DDC_DATA_UF

FUNC_TEST=YES

FUNC_TEST=YES

PCI_AD<14>

22

AIRPORT_PCI_INT_L

9 12 17 24 26 37

TPAD_F_RXD

14 24


23

FUNC_TEST=YES ADAPTER_DET

23 30

NEC_RIGHT_USB_PWREN

30 31

FUNC_TEST=YES FUNC_TEST=YES JTAG_U_TMS

FUNC_TEST=YES 5 23

DVI_HPD_UF

FUNC_TEST=YES

FUNC_TEST=YES INT_AUDIO_TO_SND

22

FUNC_TEST=YES LID_CLOSED_L

FUNC_TEST=YES

PCI_AD<15>

14 25

EIDE_OPTICAL_DATA<0>

9 12 17 24 26 37

24 37


23

SUTRO_ALS_GAIN_SW

23 30

26 32

FUNC_TEST=YES NEC_RIGHT_USB_OVERCURRENT

23 24

26 32

FUNC_TEST=YES

JTAG_U_TDI

5 23

LVDS_L0N

FUNC_TEST=YES

FUNC_TEST=YES

FUNC_TEST=YES

FUNC_TEST=YES

19 22 37

SND_SCLK

19 22 37

SND_HW_RESET_L

14 25 36

FUNC_TEST=YES COMM_RESET_L

FUNC_TEST=YES

PCI_AD<16>

9 12 17 24 26 37


24 37


9 12 17 24 26 37

FUNC_TEST=YES EIDE_OPTICAL_DATA<2>

24 37


9 12 17 24 26 37


24 37

FUNC_TEST=YES KBD_NUMLOCK_LED

14 25

FUNC_TEST=YES FUNC_TEST=YES JTAG_U_TDO_TP

FUNC_TEST=YES

FUNC_TEST=YES 5

LVDS_L0P

14 25

COMM_SHUTDOWN

FUNC_TEST=YES SUTRO_ALS_OUT

23

FUNC_TEST=YES +BATT_POS

14 25

C

JTAG_U_TCK

FUNC_TEST=YES 5 23

LVDS_L1N

FUNC_TEST=YES SND_HP_SENSE_L

19 22 37

14 25

FUNC_TEST=YES COMM_RING_DET_L

BATT_CLK

14 25 30

19 29 33 34

FUNC_TEST=YES

FUNC_TEST=YES KBD_LED1_OUT

31 38


DCDC_EN

23 24

BBANG_HRESET_L

23 38

23

FUNC_TEST=YES KBD_LED2_OUT

31

23 38

C

FUNC_TEST=YES FUNC_TEST=YES JTAG_U_TRST_L


FUNC_TEST=YES

LVDS_L1P

SND_LIN_SENSE_L

19 22 37


14 25


9 12 17 24 26 37

FUNC_TEST=YES

FUNC_TEST=YES KBD_ID

24 37

BATT_DATA

23 30

FUNC_TEST=YES COMM_TXD_L

31

MAIN_RESET_L

14 17 18 20 24 26 30

14 25

FUNC_TEST=YES FUNC_TEST=YES LVDS_L2N

FUNC_TEST=YES INT_I2C_DATA2

19 22 37


14 25

INT_I2C_CLK2

19 22 37

14 25

FUNC_TEST=YES

FUNC_TEST=YES CLKLVDS_LN

19 22 37

I293

CHGND4

38

FUNC_TEST=YES

FUNC_TEST=YES CLKLVDS_LP

19 22 37

I294

SLEEP_LED


PCI_AD<21>

12 17 24 26 37



12 17 24 26 37


FUNC_TEST=YES

FUNC_TEST=YES FUNC_TEST=YES LVDS_L2P

9 12 17 24 26 37

+3V_HALL_EFFECT

24 37

KBD_CAPSLOCK_LED

24 37

23

30 31

FUNC_TEST=YES FANR_GND

25 38

COMM_GPIO_L

KBD_FUNCTION_L

24 37

24

FUNC_TEST=YES AIRPORT_CLKRUN_L

24

14 25

FUNC_TEST=YES ROM_RW_L

FUNC_TEST=YES COMM_DTR_L

FUNC_TEST=YES COMM_RTS_L

23 30

RF_DISABLE_L_SPN 14 25

FUNC_TEST=YES

PMU_BATT_DET_L

FUNC_TEST=YES


COMM_TRXC

31 38

FUNC_TEST=YES 23 38

FUNC_TEST=YES

FUNC_TEST=YES

12 17 24 26 37

BATT_NEG

23 38

FUNC_TEST=YES

FUNC_TEST=YES


23 25

+5V_TPAD_SLEEP

24 37

FUNC_TEST=YES

FUNC_TEST=YES

FUNC_TEST=YES

FUNC_TEST=YES

9 12 24

14 25

FUNC_TEST=YES ROM_ONBOARD_CS_L

9 24

14 25

FUNC_TEST=YES FUNC_TEST=YES INT_I2C_CLK0

LVDS_U0N

PCI_AD<24>

19 22 37


9 12 17 24 26 37

FUNC_TEST=YES

FUNC_TEST=YES

FUNC_TEST=YES

FUNC_TEST=YES

FUNC_TEST=YES

11 13 23

KBD_CONTROL_L

24 37

FANL_GND

23 30

FUNC_TEST=YES

ROM_CS_L

COMM_RXD

25 38

9 12 24

14 25

FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES INT_I2C_DATA0

FUNC_TEST=YES INT_I2C_CLK1

B

13 14 25

19 22 37

17

FUNC_TEST=YES BT_USB_DM

BT_USB_DP

19 22 37

MODEM_USB_DM

19 22 37

MODEM_USB_DP


9 12 17 24 26 37



14 25 37


14 25 37

24 37

23 30

FUNC_TEST=YES PMU_KB_RESET_L

25

CLK33M_AIRPORT


9 12 17 24 26 37

9 12 17 24 26 37


9 12 17 24 26 37


I271

FANR_PWM

FUNC_TEST=YES

FUNC_TEST=YES

25

AIRPORT_IDSEL PWR_BUTTON_L

23 30

TMDS_DN<0>

FUNC_TEST=YES TMDS_DP<0>

20 22 37

20 22 37

20 22 37

20 22 37

FUNC_TEST=YES KBD_SHIFT_L

24 37

FUNC_TEST=YES KBD_X<0>

24 37

I272

FANL_PWM FUNC_TEST=YES RJ45_DP<0>

23 30

FUNC_TEST=YES

25

FUNC_TEST=YES +PBUS

KBD_X<1>

FUNC_TEST=YES

+24V_PBUS

23 30

38

FUNC_TEST=YES

27 37

FUNC_TEST=YES

GPU_VCORE

23 30

A

PCI_AD<31>

EIDE_OPTICAL_DMA_RQ

9 12 17 24 26 37

LVDS_DDC_CLK

19 22

PCI_AD<2>

9 12 17 24 26 37

19 22

PCI_AD<3>

9 12 17 24 26 37

22

TV_GND1

PCI_AD<4>

9 12 17 24 26 37

PCI_AD<5>

PCI_TRDY_L

EIDE_OPTICAL_DMAACK_L

12 17 24 26 37

PCI_IRDY_L

EIDE_OPTICAL_ADDR<0>

12 17 24 26 37

9 12 17 24 26 37

PCI_DEVSEL_L

KBD_X<3>

24 37


12 17 24 26 37


22 38

PCI_AD<6>

9 12 17 24 26 37

PCI_STOP_L

KBD_X<4>

24 37

I291

FUNC_TEST=YES SND_AMP_MUTE

27 37

SND_HP_MUTE_INV

KBD_X<5>

24 37

KBD_X<6>

FUNC_TEST=YES KBD_X<7>

KBD_X<8>

+1_8V_MAIN

14 25

FUNC_TEST=YES 38

MOD_SYNC

I278

27 37

+3V_PMU

23 30

14 25

FUNC_TEST=YES 38

FUNC_TEST=YES

23 30

22 38

1778_VFB

I280

27 37

FUNC_TEST=YES +12_8V_INV

29 38

23 25 30 33 35

FUNC_TEST=YES

+5V_DDC_SLEEP

23 30

FUNC_TEST=YES FW_TPO0R FUNC_TEST=YES VCORE_VID0

SLEEP

I279

27 37

FUNC_TEST=YES

19 38

22 38

A

I281

FUNC_TEST=YES


23 30

FUNC_TEST=YES SRCLK_TP I287

I282

FUNC_TEST=YES VCORE_VID1

VCORE_MUX_EN I286

34

26

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

25

FUNC_TEST=YES SRMOD_TP I288

I283

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

26

25

FUNC_TEST=YES TEB_TP

26

I285


FUNC_TEST=YES

5

MOD_DTO

I277

FUNC_TEST=YES

FUNC_TEST=YES

6

FUNC_TEST=YES

FUNC_TEST=YES

FUNC_TEST=YES 24 37

14 25

34 38

27 37

FUNC_TEST=YES

RJ45_DN<3>

24 37

MOD_CLKOUT

I276

VCORE_FB

FUNC_TEST=YES

I290

7

14 25

FUNC_TEST=YES

27 37

23 30

RJ45_DP<3>

24 37

5 6 34 38

FUNC_TEST=YES

I289

8

MOD_BITCLK

I275

U_VCORE_SLEEP

FUNC_TEST=YES

RJ45_DN<2>

FUNC_TEST=YES I292

23 30

FUNC_TEST=YES RJ45_DP<2>

FUNC_TEST=YES

FUNC_TEST=YES

FUNC_TEST=YES

TV_GND2

23 30

FUNC_TEST=YES RJ45_DN<1>

FUNC_TEST=YES

FUNC_TEST=YES 12 17 24 26 37

5 23 39

18 19 38

FUNC_TEST=YES

FUNC_TEST=YES

FUNC_TEST=YES

FUNC_TEST=YES

FUNC_TEST=YES 22 38

FUNC_TEST=YES 22 37

KBD_X<2>

24 37

FUNC_TEST=YES

FUNC_TEST=YES

FUNC_TEST=YES

BRIGHT_PWM

EIDE_OPTICAL_RD_L

12 17 24 26 37

FUNC_TEST=YES

FUNC_TEST=YES

LVDS_DDC_DATA

FUNC_TEST=YES PCI_FRAME_L

FUNC_TEST=YES

FUNC_TEST=YES TMDS_CONN_CLKN

9 12 17 24 26 37

JTAG_U_TRST_L

I274

FUNC_TEST=YES RJ45_DP<1>

B

14 25

I273

FUNC_TEST=YES

FUNC_TEST=YES

FUNC_TEST=YES

FUNC_TEST=YES


9 12 17 24 26 37


9 12 24

FUNC_TEST=YES INT_MOD_DTI

FUNC_TEST=YES 24 37

ROM_OE_L 38

27 37

FUNC_TEST=YES RJ45_DN<0>

FUNC_TEST=YES



CLKLVDS_UP

FUNC_TEST=YES

FUNC_TEST=YES TMDS_DN<2>

19 22 37


FUNC_TEST=YES


19 22 37


FUNC_TEST=YES

FUNC_TEST=YES TMDS_DN<1>

FUNC_TEST=YES CLKLVDS_UN

24

23 25


12 24 36

30

FUNC_TEST=YES

FUNC_TEST=YES

PCI_AD<27>

FUNC_TEST=YES

LVDS_U2P

9 12 17 24 26 37


FUNC_TEST=YES KBD_OPTION_L

FUNC_TEST=YES

PCI_AD<26>

14 24 37

FUNC_TEST=YES

LVDS_U2N

KBD_COMMAND_L

24 37

FUNC_TEST=YES

FUNC_TEST=YES

LVDS_U1P

FUNC_TEST=YES

FUNC_TEST=YES CBUS_DET_2_L

19 22 37

FUNC_TEST=YES 17


9 12 17 24 26 37

FUNC_TEST=YES

LVDS_U1N

FUNC_TEST=YES FANL_TACH

FUNC_TEST=YES

PCI_AD<25>

19 22 37

FUNC_TEST=YES

FUNC_TEST=YES CBUS_DET_1_L

LVDS_U0P


FUNC_TEST=YES INT_I2C_DATA1

FUNC_TEST=YES


4

TEST_TP

26

I284

SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SHT NONE

2

REV.

051-6598

SCALE

VCORE_VID4

3

D

OF

01

39 44 1

8

7

6

5

4

3

2

1

REVISION HISTORY 12/11/03 1) 2) 3) 4) 5) 6) 7) 8) 9)

IMPORTED Q41 PRODUCTION RELEASE SCHEMATIC CHANGED U (U43) TO A7PM CHANGED PLL CONFIG STUFFING FOR NEW U CHANGED U44 TO M11-CSP64 SYMBOL ADDED U AVDD LDO (U6) ADDED R284 AND R604 TO ADD OPTION FOR PD_L OF U42 (CLOCK CHIP) TO BE DRIVEN BY JTAG_ASIC_TDO FROM INTREPID ADDED R608 TO DISCONNECT INT_GPIO0 FROM CG_FSEL CHANGED JTAG_ASIC_TDO_TP TO JTAG_ASIC_TDO AND MOVED IT TO INTREPID’S TDO CHANGED JTAG_ASIC_TDI TO CONNECT TO ETHERNET PHY’S TDI

12/15/03

D

10) 11)

D

CHANGED PIN 4 (DCDC_EN) ON J11 TO NEC_RIGHT_USBOVERCURRENT CHANGED PIN 11 OF J11 TO NC

12/16/03 12) 13) 14) 15) 16) 17)

ADDED R633 AS PULLUP ON JTAG_ASIC_TDI CHANGED U_TEMP_DM TO U_THERM_DM CHANGED U_TEMP_DP TO U_THERM_DP CHANGED GPU_THERM_DP TO GPU_THERM_DP_TP CHANGED GPU_THERM_DM TO GPU_THERM_DM_TP FIXED MISSED CONNECTION WITH MAXBUS_SLEEP TO U

12/17/03 18) 19) 20)

CHANGED R657 (EXTPLL_SDWN_POL BOOT STRAP) TO NO STUFF AND REMOVED NO STUFF FROM R153 UPDATE DIFF NET_SPACING_TYPE PROPERTY ON POWER SUPPLY SENSE AND THERMAL DIODE DIFF PAIRS CHANGED FIREWIRE OSCILLATOR (G1) TO NEW PREFERRED SUNNY PART

12/18/03 21)

CHANGED MAX VIA COUNT ON ALL AGP STB NETS TO 5 TO CLEAR DRCS

** RELEASED FOR EVT **

C

C

B

B

A

A

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

D

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-6598 OF

01

40 44 1

8

D

*** Signal Cross-Reference for the entire design ***

3V_SNSM 3V_SNSP

33C4< 37A2> 33C4< 37A2>

+1_0V_MARVELL +1_5V_AGP

27D2< 38B3> 12C5< 12D1< 12D4< 15D5< 16C8< 18C6< 18D6< 19A8< 19B4<> 19D5<> 21B8< 21D6< 38C3> +1_5V_AGP_GPU 21C5< 38C3> +1_5V_AGP_NECK 19B4<> 38B3> +1_5V_GPU_VDD15 19D3< 38C3> +1_5V_INTREPID_PLL 8D6< 12D4< 12D8< 14D6<> 38D3> +1_5V_INTREPID_PLL1 14C3< 38D3> +1_5V_INTREPID_PLL2 14D3< 38D3> +1_5V_INTREPID_PLL3 14D3< 38D3>

3V_SW 3V_TG 3V_VOSNS 5V_BG 5V_BOOST

33C4<> 38D1> 33D4<> 33C4<> 33C5<> 33C5<>

AGP_SBA<5> AGP_SBA<6> AGP_SBA<7> AGP_SB_STB AGP_SB_STB_L AGP_ST<0> AGP_ST<1>

5V_BOOST_ESR 5V_HD_PWREN 5V_ITH 5V_ITH_RC 5V_RSNS 5V_RUNSS

33D6<> 33A8<> 33C5<> 33C6< 33D7< 38D1> 33C5<

AGP_ST<2> 12A2<> 18C6< AGP_STOP_L 12B2<> 12C2< 18B7<> 37D5> AGP_STP_L 18C6< AGP_SUS_STAT_L_PU 18C6< AGP_TRDY_L 12B2<> 12C2< 18B7<> 37D5> AGP_WBF_L 12A4<> 12B2< 18B7>

+1_5V_INTREPID_PLL4 +1_5V_INTREPID_PLL5 +1_5V_INTREPID_PLL6 +1_5V_INTREPID_PLL7 +1_5V_INTREPID_PLL8

+1_5V_LDO 35D8< 38D6> +1_5V_MAIN 38D6> +1_5V_SLEEP 38D6> +1_5V_SLEEP_NECK 21A3<> 38B3> +1_5V_SLEEP_VIN 35D8<> 38D6> +1_8V_ATI_PVDD 19C5<> 21B6< 21B6< 21D6<> 38C3> +1_8V_ATI_TPVDD 21D2<> +1_8V_DVO_F 21B2< +1_8V_GPU 18A7< 19D8< 20A5< 21A2< 21A6< 21B1< 21B6< 21C8< 21D6< 21D8< 38C3> +1_8V_GPU_AVDD 21D5< 38C3>

5V_SLEEP_PWREN 5V_SNSM 5V_SNSP 5V_SW 5V_TG 5V_VOSNS 1625_BG 1625_BST 1625_BST_ESR 1625_COMP 1625_DIV 1625_ENABLE 1625_ENABLE_L 1625_EXTVCC 1625_FCB 1625_INTVCC

33A8<> 33C5< 37A2> 33C5< 37A2> 33C5<> 38D1> 33C5<> 33C5<> 32C5<> 32C5< 32C5<> 31D2< 32C6< 32C8< 32D7<> 32D6<> 32D5<> 38D1> 32C6< 32C5<> 38D1>

+1_8V_GPU_AVDDQ 21D4< 21D7< 38C3> +1_8V_GPU_MEMPLL 21B5< 38C3> +1_8V_GPU_PLL 21D5< 38C3> +1_8V_GPU_PNLIO 21A5< 38C3> +1_8V_GPU_PNLPLL 21B5< 38C3> +1_8V_GPU_TP_PLL 21B4< 21D1<

1625_RUNSS 1625_SGND 1625_TG 1625_VFB 1625_VIN 1625_VSW

32C6< 32B7<> 38D1> 32C5<> 32B5<> 32C6< 38D1> 32C4<> 38D1>

+1_8V_GPU_VDDDI 21C7< 21D4< 38C3> +1_8V_MAIN 38D6> 39A2> +1_8V_MAIN_LX_F 35A4<> +1_8V_PVDD_NECK 19B5<> 38B3> +1_8V_SLEEP 38D6> +1_8V_SLEEP_NECK 21A3<> 38B3> +1_95V_FW_DVDD 28C4< 28C7<> 28D5< 38A3> +1_95V_FW_DVDD_PORT1 28D6< 38A3> +1_95V_FW_DVDD_RX0 28C5< 38A3> +1_95V_FW_DVDD_TX0 28C5< 38A3> +1_95V_FW_PLL400VDD 28D5< 38A3>

1772_ACIN 1772_ACOK_L 1772_BST 1772_BST_ESR 1772_CCI 1772_CCS 1772_CCV 1772_CCV_RC 1772_CELLS 1772_CLS 1772_CSIN

31B5< 31B5<> 31C4<> 31B4<> 31C3< 31B5<> 31B5< 31B5<> 31B5< 31B4< 31A4< 31B4<> 37A2>

+1_95V_FW_PLL500VDD 28D5< 38A3> +1_95V_FW_PLLVDD 28D5< 28D7<> 38A3> +2_5V_CG_MAIN 14C6< 38A3> +2_5V_GPU 21A7< 21B6< 21D3< 21D7< 21D8< 38B3>

1772_CSIP 31B4<> 37A2> 1772_CSSN 31C5< 37A2> 1772_CSSP 31C5< 37A2> 1772_DCIN 31B5< 38C6> 1772_DHI 31B4<> 1772_DLO 31B4<> 1772_DLOV 31B4<> 38C6> 1772_GND 31A5<> 38C6> 1772_ICHG 31B5<> 1772_ICTL 31B5<> 1772_IINP 31B5< 1772_LDO 31C4<> 38C6> 1772_LX 31B4<> 38C6> 1772_REF 31B5<> 1772_VCTL 31B5< 1778_BG 19A5<> 38B1> 1778_BST 19A5<> 38B1> 1778_BST_RC 19A4<> 38B1> 1778_FCB 19A5< 38B1> 1778_GND 19A5< 19A7<> 38B1> 1778_ION 19A5< 38B1> 1778_ITH 19A5<> 38B1> 1778_ITH_RC 19A7< 38B1> 1778_SHDN_L 19A6< 1778_SHDN_L_D3COLD 19A7<> 1778_TG 19A5<> 38B1> 1778_VCC 19A5<> 38B1> 1778_VFB 19A2< 19A5< 38B1> 39A1> 1778_VIN 19A5< 38B1> 1778_VRNG 19A5< 38B1> 3405_MODE 27D5< 3405_VFB 27D4<> 3707_FCB 33C5<

+2_5V_GPU_A2VDD +2_5V_GPU_PNLIO +2_5V_INTREPID +2_5V_MAIN +2_5V_MARVELL

14D3< 38D3> 12D3< 38D3> 12D6< 38D3> 8D5< 38D3> 14D3< 38D3>

21D4< 21D7< 38C3> 21A5< 38C3> 9A8< 10D3< 10D5< 10D6< 10D8< 15D7< 16B8< 38D3> 38D6> 27B8< 27C4<> 38B3>

+2_5V_MARVELL_AVDD 27C4< 38B3> +2_5V_SLEEP 38D6> +2_5V_SLEEP_NECK1 19C4<> 38B3> +2_5V_SLEEP_NECK2 21A3<> 38B3> +3V_ATI_OSC_SLEEP 18D2< 38C3>

C

+3V_ATI_SS 18B2< 38C3> +3V_CG_PLL_MAIN 14C6< 38A3> +3V_FW 28A3< 28D7<> 29D5< 38A3> +3V_FW_AVDD 28C6< 38A3> +3V_FW_AVDD_PORT0 28C6< 38A3> +3V_FW_AVDD_PORT1 28C6< 38A3> +3V_FW_AVDD_PORT2 28D6< 38A3> +3V_FW_ESD 29B3<> 29D2<> 38B3> +3V_FW_ESD_ILIM 29D4< 38B3> +3V_FW_UF 28D7<> 38A3> +3V_GPU 12D1< 18B8< 18C5< 18C7< 18D6< 19C4< 19C6< 19C7< 19D7< 21A6< 21B1< 38C3> +3V_GPU_FLT 21B2< 38C3> +3V_GPU_SI 20C4< 20C8< 20D8< +3V_HALL_EFFECT 23C6<> 38B6> 39C4> +3V_INTREPID_USB 14C3< 38D3>

B

+3V_LCD +3V_LCD_SW +3V_MAIN +3V_NEC_VDD +3V_PMU +3V_PMU_AVCC +3V_PMU_ESR +3V_PMU_RESET +3V_SI_AVCC +3V_SI_PLLVCC +3V_SI_VCC

22B4<> 38B6> 22A4<> 38B6> 38D6> 26D7< 26D7< 38A3> 38D6> 39A2> 25A4< 30B6< 30D5<> 38C6> 32A2< 38C6> 30B7< 34A3<> 20C7< 38B3> 20C7< 38B3> 20C6< 38B3>

+3V_SLEEP +3V_SLEEP_NECK +3V_SLP_OK_L +3V_SLP_ON +4_6V_BU +4_85V_ESR +4_85V_RAW +5V_DDC_SLEEP +5V_DDC_SLEEP_UF +5V_HD_SLEEP +5V_INV_SW +5V_INV_UF_SW +5V_MAIN +5V_SLEEP +5V_SOUND_SLEEP +5V_TPAD_SLEEP +12_8V_INV +24V_PBUS +ADAPTER +ADAPTER_ILIM +ADAPTER_OR_BATT +ADAPTER_SENSE +ADAPTER_SW +BATT +BATT_14V_FUSE +BATT_24V_FUSE +BATT_POS

38D6> 21A3<> 38B3> 33B4<> 33A5<> 32A3<> 33B7< 38C6> 32A4< 38C6> 30B4< 32A4<> 38C6> 22D3<> 22D5<> 38B6> 39A2> 22D6< 38B6> 24D1<> 33A7<> 38C6> 22B1<> 38B6> 39D1> 22B2<> 38B6> 38D6> 38D6> 38B6> 23C7<> 38B6> 39C4> 22B1<> 38B6> 39A2> 38D6> 39B2> 31D8<> 32B7< 38D6> 32B6<> 38C6> 32A5<> 38C6> 31D5<> 38C6> 31D6<> 38C6> 38D6> 31D1<> 38C6> 31B1< 31D2<> 38C6> 31A4<> 38C6> 39C3>

+BATT_RSNS +BATT_VSNS +FW_FUSE +FW_PWR_OR +FW_PWR_PORTA +FW_SW +FW_VP0 +FW_VP1 +GPU_MCLK +GPU_MEM

31B2< 38C6> 31A4< 38C6> 29D7<> 38A3> 28B8< 28D8<> 29D5<> 38A3> 29C5< 38A3> 29D5<> 38A3> 29C2<> 38A3> 29A3<> 38A3> 21C7< 21D4< 38C3> 18A6<> 18B8< 21B4< 21B7< 21C6< 21C8< 21D2< 38C3> +GPU_MEMCORE 21C5< 38C3> +GPU_VDD15_NECK 19B5<> 38B3> +GPU_VDD15_UF 19B5<> 19D4<> 38C3> +HD_LOGIC_SLEEP 24C2<> 38C6> +PBUS 38D6> 39B2> +VCC_CBUS_SW 17B1<> 17B2<> 17D2<> 38D3> +VPP_CBUS_SW 1V20_REF 1V65_REF 1_5V_2_5V_OK 1_5V_BOOST

A

6

7

17B1<> 17B2<> 17D2<> 38C3> 31C7< 32C8< 38D1> 31A5< 35C5> 38B1> 35C6<> 38C1>

1_5V_BST 35C5<> 38C1> 1_5V_DH 35C5<> 38C1> 1_5V_DL 35B5<> 38C1> 1_5V_FB 35B5< 35B7< 38C1> 1_5V_ILIM 35C5<> 38C1> 1_5V_LX 35B5<> 38C1> 1_5V_SLEEP_EN_L 35C7<> 35D7<> 1_8V_SLEEP_PWREN_L 35A3<> 1_8V_SW 35A5<> 38A1> 1_8V_VFB 38A1> 2_5V_BOOST 35C4<> 38D1> 2_5V_BST 35C4<> 38D1> 2_5V_DH 35C4<> 38D1> 2_5V_DL 35B4<> 38D1> 2_5V_ILIM 35C5<> 38C1> 2_5V_LX 35B4<> 38D1> 2_5V_SLEEP_PWREN_L 35C2<> 2_34V_REF 30A4< 3V_5V_OK 33B4<> 35A8<> 35D6< 3V_5V_OK_INV 35A8<> 3V_BG 33C4<> 3V_BOOST 33C4<> 3V_BOOST_ESR 3V_ITH 3V_ITH_RC 3V_PMU_VTAP 3V_RSNS 3V_RUNSS 3V_SLEEP_PWREN_L

33D3<> 33C4<> 33C3< 32B3< 33D2< 38D1> 33C4< 33A3<>

3707_FSET 33C5< 3707_INTVCC 33D4<> 38D1> 3707_SGND 33B5<> 38D1> 3707_STBY 33C5<> A29_CLS_ADJ 31A5<> A29_CURRENT_ADJ 31C4<> A29_DETECT 30A2< 31A5<> 31C4<> A29_DET_L 30A3< AB_SEL_LOW 34A6<> AC_DIV 31C8< AC_ENABLE_GATE 31D6<> AC_ENABLE_L 31C6<> AC_GTR_18V 31C4<> AC_IN 27B8<> 29C7< 30B3< 31C5<> 31C7<> AC_IN_FW_CNTL 29C7<> AC_IN_L 31C2<> 31C6<> AC_IN_L_RC 31C2<> ADAPTER_DET 30A4< 31D8<> 39C2> ADAPTER_I_REG 31D3<> ADT7460_ADR_EN_L 25B3<> ADT7460_FAN1_PWM 25B3<> ADT7460_FAN2_PWM 25B3<> ADT7460_THERM 25A5<> 25B3<> ADT7460_VCC 25C4< ADT7460_VCORE_MON 5C8<> 25B4<> AGP8X_DET_PU 18C6<> AGP_AD<0> 12D2<> 18C7<> AGP_AD<15..0> 37D5> AGP_AD<1> 12C2<> 18C7<> AGP_AD<2> 12C2<> 18C7<> AGP_AD<3> 12C2<> 18C7<> AGP_AD<4> 12C2<> 18C7<> AGP_AD<5> 12C2<> 18C7<> AGP_AD<6> 12C2<> 18C7<> AGP_AD<7> 12C2<> 18C7<> AGP_AD<8> 12C2<> 18C7<> AGP_AD<9> 12C2<> 18C7<> AGP_AD<10> 12C2<> 18C7<> AGP_AD<11> 12C2<> 18C7<> AGP_AD<12> 12C2<> 18C7<> AGP_AD<13> 12C2<> 18C7<> AGP_AD<14> 12C2<> 18C7<> AGP_AD<15> 12C2<> 18C7<> AGP_AD<16> 12C2<> 18C7<> AGP_AD<31..16> 37D5> AGP_AD<17> 12C2<> 18C7<> AGP_AD<18> 12C2<> 18C7<> AGP_AD<19> 12C2<> 18C7<> AGP_AD<20> 12C2<> 18C7<> AGP_AD<21> 12C2<> 18C7<> AGP_AD<22> 12C2<> 18C7<> AGP_AD<23> 12C2<> 18C7<> AGP_AD<24> 12C2<> 18C7<> AGP_AD<25> 12C2<> 18D7<> AGP_AD<26> 12C2<> 18D7<> AGP_AD<27> AGP_AD<28> AGP_AD<29> AGP_AD<30> AGP_AD<31> AGP_AD_STB<0> AGP_AD_STB<1> AGP_AD_STB_L<0> AGP_AD_STB_L<1> AGP_ATI_RESET_L AGP_ATI_VREF AGP_ATI_VREFG AGP_BUSY_L AGP_CBE<0> AGP_CBE<1..0> AGP_CBE<1> AGP_CBE<2> AGP_CBE<3..2> AGP_CBE<3> AGP_DEVSEL_L AGP_FRAME_L AGP_GNT_L AGP_INT_L AGP_IRDY_L AGP_PAR AGP_PIPE_L AGP_RBF_L AGP_REQ_L AGP_SBA<0> AGP_SBA<7..0> AGP_SBA<1> AGP_SBA<2> AGP_SBA<3>

12B2<> 18D7<> 12B2<> 18D7<> 12B2<> 18D7<> 12B2<> 18D7<> 12B2<> 18D7<> 12A2<> 12B2< 18D6<> 37D5> 12A2<> 12B2< 18D6<> 37D5> 12A2<> 12B2< 18D6<> 37D5> 12A2<> 12A2< 18D6<> 37D5> 18B7< 18B7< 18B7< 12C4<> 12D2< 18D6> 12B2<> 18B7<> 37D5> 12B2<> 18B7<> 12B2<> 18B7<> 37D5> 12B2<> 18C7<> 12B2<> 12C2< 18B7<> 37D5> 12B2<> 12C2< 18B7<> 37D5> 12C2< 12D2<> 18B7< 37D5> 14B5<> 18B7<> 12B2<> 12C2< 18B7<> 37D5> 12B2<> 18B7> 37D5> 12A2<> 12B2< 12A2<> 12C2< 18C6> 37D5> 12C2< 12D2<> 18B7<> 37D5> 12B2< 18C6> 37D5> 12B2<> 18C6> 12B2<> 18C6> 12B2<> 18C6>

AGP_SBA<4>

12B2<> 18C6>

12B2<> 12B2<> 12B2<> 12B2<> 12A2<> 12A2<> 12A2<>

CG_SYSCLK_EN CHARGE_DISABLE

18C6> 18C6> 18C6<> 12B2< 18C6<> 37D5> 12A2< 18C6<> 37D5> 18C6< 18C6<

14A6< 14B7< 31A7<>

19C5< 22C3<> 38C3>

GPU_MEM_IO_FLT GPU_R GPU_SSCLK_IN GPU_SSCLK_UF GPU_THERM_DM_TP

21C2< 38C3> 19D6<> 22D8< 36B1> 36C1> 18A6<>

23B7<> 23B7<> 23B7<> 23B7<> 23B7<> 23B7<> 22A6< 22A5<> 27B5<> 27B5<> 27B5> 24B2<> 24B2<>

LID_CLOSED_L LM2594_IN LT1962_INT_ADJ LT1962_INT_BYP LTC1625_ITH

ENET_LINK_TXD<7..0> 37A5> ENET_LINK_TXD<1> 13B4< 13D5> ENET_LINK_TXD<2> 13B4< 13D5> ENET_LINK_TXD<3> 13B4< 13D5> ENET_LINK_TXD<4> 13B4< 13D5> ENET_LINK_TXD<5> 13B4< 13D5> ENET_LINK_TXD<6> 13A4< 13D5> ENET_LINK_TXD<7> 13A4< 13D5> ENET_LINK_TX_EN 13D5<> 37A5> ENET_LINK_TX_ER 13D5<> 37A5> ENET_MDC 13C5> 27B7< 37A5>

GPU_VCORE_CNTL_L 19A3< 19B7<> GPU_VCORE_NECK 19B5<> 38B3> GPU_VCORE_PWR_SEQ 19A8<> GPU_VCORE_SEQ 19A8< GPU_VCORE_SEQ_L 19A8< GPU_VCORE_SW 19A4<> 38B1> GPU_VCORE_VDDCI 18A5< 38C3> GPU_Y 19D6<> 22B8< HD_ADDR<0> 24C2<> 24C3< HD_ADDR<2..0> 37C5> HD_ADDR<1> 24C2<> 24C3< HD_ADDR<2> 24B3< 24C1<> HD_CS0_L 24C2<> 24C3< 37B5> HD_CS1_L 24B3< 24C1<> 37B5> HD_DATA<0> 24C2<> 24D3< HD_DATA<15..0> 37C5>

ENET_MDIO 13C5<> 27B7<> 37A5> ENET_PHY_TXD<0> 13B5< 27C7< ENET_PHY_TXD<7..0> 37A5> ENET_PHY_TXD<1> 13B5< 27C7< ENET_PHY_TXD<2> 13B5< 27C7< ENET_PHY_TXD<3> 13B5< 27C7<

HD_DATA<1> HD_DATA<2> HD_DATA<3> HD_DATA<4> HD_DATA<5> HD_DATA<6>

U_PLL_FS01 7C4< U_PLL_FS10 7C4< U_PLL_STOP_BASE 7C7< U_PLL_STOP_OC 7C4<> 7C8<> 30B6<> U_PMONIN_L 5A4< 5C2< U_PULLDOWN 5A2< 5A4< 5A4< 5C7<> U_PULLUP 5A4< 5A4< 5C2< U_QACK_L 5B4< 8B6<> 36D5> U_QREQ_L 5B4> 8B6< 8C2< 36D5> U_SHD0_L 5A7<> 5D2< U_SHD1_L 5A7<> 5D2<

ENET_PHY_TXD<4> ENET_PHY_TXD<5> ENET_PHY_TXD<6> ENET_PHY_TXD<7> ENET_PHY_TX_EN ENET_PHY_TX_ER ENET_RSET ENET_RST_L ENET_RX_DV ENET_RX_ER ENET_VSSC

9B8<> 10C1<> 9B8<> 10C1<> 9B8<> 10C1<> 9B8<> 10C1<> 9B8<> 10C1<> 9B8<> 10C1<> 36A5> 9B8<> 10C1<> 9B8<> 10C1<> 9B8<> 10C1<> 9B8<> 10C1<> 9B8<> 10B1<> 9B8<> 10B1<>

23A7<> 39C4> 28D8<> 38B3> 14D6< 14D6<> 31D3<>

MEM_DATA<63> MEM_DQM<0> MEM_DQM<1> MEM_DQM<2> MEM_DQM<3..2>

9B8<> 9C6<> 9C6<> 9C6<> 36B5>

10B1<> 10C7<> 36C5> 10B7<> 36C5> 10C5<>

LTC1962_1V5_VIN LTC1962_1V5_VOUT LTC1962_INT_VIN LTC1962_L3_VIN LTC1962_L3_VOUT LTC3405_SW LTC3411_GND LTC3411_ITH LTC3411_ITH_RC LTC3411_SHDN LTC3411_SYNC

38A1> 38A1> 14D7<> 38A1> 38A1> 38A1> 27D4<> 38B3> 38A1> 38A1> 38A1> 38A1> 38A1>

MEM_DQM<3> MEM_DQM<4> MEM_DQM<5..4> MEM_DQM<5> MEM_DQM<6> MEM_DQM<7> MEM_DQS<0> MEM_DQS<1> MEM_DQS<2> MEM_DQS<3..2> MEM_DQS<3>

9C6<> 9C6<> 36B5> 9C6<> 9C6<> 9C6<> 9C6<> 9C6<> 9C6<> 36B5> 9C6<>

10B5<> 10C3<>

24C2<> 24D3< 24D2<> 24D3< 24D2<> 24D3< 24C3< 24D2<> 24C3< 24D2<> 24C3< 24D2<>

LTC3411_VCC LTC3412_GND LTC3412_ITH LTC3412_ITH_RC LTC3412_PGOOD LTC3412_RT

38B1> 35A6<> 35A6<> 35A6< 35A4<> 35A6<

MEM_DQS<4> MEM_DQS<5..4> MEM_DQS<5> MEM_DQS<6> MEM_DQS<7> MEM_MUXSEL_H<0>

9C6<> 36B5> 9C6<> 9C6<> 9C6<> 9B6<>

10C3<>

HD_DATA<7> HD_DATA<8> HD_DATA<9> HD_DATA<10> HD_DATA<11> HD_DATA<12> HD_DATA<13> HD_DATA<14> HD_DATA<15> HD_DIOR_L HD_DIOW_L

24C3< 24D2<> 24C3< 24D1<> 24C3< 24D1<> 24C3< 24D1<> 24D1<> 24D3< 24B3< 24D1<> 24B3< 24D1<> 24C1<> 24C3< 24B3< 24C1<> 24A3< 24C2<> 37B5> 24A3< 24C1<> 37B5>

LTC3412_RUNSS LTC3412_SYNC LTC3412_VFB LTC3412_VFB_DIV LTC3707_START_RC LVDS_DDC_CLK LVDS_DDC_DATA LVDS_L0N LVDS_L0P LVDS_L1N LVDS_L1P

35A6<> 35A6<> 35A6<> 35A6< 33B6<> 19C5<> 22B5<> 39A7> 19C5<> 22B5<> 39A7> 19B5> 22B4<> 37C2> 39C7> 19B5> 22B4<> 37C2> 39C7> 19B5> 22B4<> 37C2> 39C7> 19B5> 22B4<> 37C2> 39C7>

EXT_SWING 20A5<> FANL_GND 25A3<> 38B6> 39B3> FANL_PWM 25A3<> 25B2<> 39B3> FANL_TACH 25A3<> 25B2< 39B3> FANR_GND 25B2<> 38B6> 39B3> FANR_PWM 25A2<> 25B1<> 39B3> FANR_TACH 25B2< 25B2<> FB_4_85V_BU 32A5< FP_PWR_EN 19C6<> 22A6< 22B3<> FP_PWR_EN_L 22B3<> FWB_TPB0 28A3< FWB_TPB1 28A4< FWPLL_BYP 28C8<> FW_BIAS0 28A5<> FW_BIAS1 28A5<> FW_BMODE 28B7< FW_CORE_ADJ 28C8< FW_CORE_BYP 28C7<> FW_S 28B7< FW_INPUT_PD 28A7< FW_LINK_CNTL<0> 13C3<> 28C3< FW_LINK_CNTL<1..0> 37A5>

HD_DMACK_L HD_DMARQ HD_INTRQ HD_IOCHRDY HD_RESET_L HIGH_VCORE HIGH_VCORE_DIV HPD_4V_REF HPD_BASE HPD_ON HPD_ON_RC HPD_PWR_SNS_EN HPD_PWR_SW IAC_FB IAC_RC_COMP INTREPID_ACS_REF

24A3< 24C2<> 37B5> 13C6< 24C2<> 37B5> 13C6< 24C1<> 37B5> 24A3< 24C1<> 37B5> 24A3< 24D2<> 37B5> 19A2<> 19A3< 22C3< 22C1< 22C2<> 22C2< 19C7<> 22C3<> 22C2<> 31D4< 31D4< 8A6<

LVDS_L2N LVDS_L2P LVDS_L3N_TP LVDS_L3P_TP LVDS_U0N LVDS_U0P LVDS_U1N LVDS_U1P LVDS_U2N LVDS_U2P LVDS_U3N_TP LVDS_U3P_TP MAIN_RESET_L

19B5> 22B4<> 37C2> 39C7> 19B5> 22B4<> 37C2> 39C7> 19B5> 19B5> 19C5> 22A4<> 37C2> 39B7> 19C5> 22A4<> 37C2> 39B7> 19C5> 22A4<> 37C2> 39B7> 19C5> 22A4<> 37C2> 39B7> 19B5> 22A4<> 37B2> 39B7> 19B5> 22A4<> 37B2> 39B7> 19B5> 19B5> 14C7< 17A7< 17D5< 18C8< 20B8< 24D6<> 26B8< 30D4<> 30D7< 39C1> 35B1< 35B4< 35B5<> 35C5< 38C1>

MEM_MUXSEL_H<1..0> 36A5> MEM_MUXSEL_H<1> 9B6<> 10A4< MEM_MUXSEL_L<0> 9B6<> 10A6< MEM_MUXSEL_L<1..0> 36A5> MEM_MUXSEL_L<1> 9B6<> 10A4< MEM_RAS_L 9A5< 9C6<> 36A5> MEM_WE_L 9A5< 9C6<> 36A5> MLB_ALS_GAIN_SW 23C4<> 23C8<> MLB_ALS_OP_COMP 23D7< MLB_ALS_OP_IN 23D7< MLB_ALS_OUT 23C4<> 23D6< MLB_ALS_OUT_FB 23D7<> MLB_PHOTODIODE 23D8<> MODEM_USB_DM 14B1< 25C3<> 37A2> 39B6> MODEM_USB_DP 14B1< 25C3<> 37A2> 39B6> MOD_BITCLK 14A2< 25C3<> 39B1> MOD_CLKOUT 14A2< 25C4<> 39A1> MOD_DTO 14A2< 25C4<> 39A1> MOD_SYNC 14A2< 25C3<> 39A1> MPIC_U_INT_L 5B2< 5B4< 14B5> NEC_AMC_TP 26A5< NEC_AVDD 26D6< 38A3> NEC_AVSS_F 26A5< 26B4< NEC_CRUN_L 26A7<> NEC_IDSEL 26B7< NEC_IO_RESET_L 26B7< 26B7< NEC_LEFT_USB_OVERCURRENT 24B2<> 26C1< 39D1>

U_SMI_L U_SRESET_L U_SRWX_L U_TA_L U_TBEN

5B4< 5B2< 5A4< 5B4< 5B4<

5A7> 8B6<> 36D5> 5B4< 8A4<> 8C2< 36D5> 6A6<> 25A6< 6A6<> 25A6< 5A7> 8B6<> 36D5> 5A7> 8B6<> 5A7> 8B6<> 5C7<> 8D2< 8D6<> 36D5> 5A7<> 8B6<> 36C5>

FW_LINK_CNTL<1> 13C3<> 28C3< FW_LINK_DATA<0> 13D3<> 28B8< FW_LINK_DATA<7..0> 37A5> FW_LINK_DATA<1> 13D3<> 28B8< FW_LINK_DATA<2> 13D3<> 28B8< FW_LINK_DATA<3> 13D3<> 28A8< FW_LINK_DATA<4> 13C3<> 28A8< FW_LINK_DATA<5> 13C3<> 28A8< FW_LINK_DATA<6> 13C3<> 28A8< FW_LINK_DATA<7> 13C3<> 28A8< FW_LINK_LREQ 13C3<> 37A5> FW_LKON 13C3<> 28B5<> FW_OSC 28A4< 36A1> FW_OSC_EN 28A3< FW_PC_PD 28B7< FW_PC_PU 28B7< FW_PHY_CNTL<0> 28B4<> 28C3< FW_PHY_CNTL<1..0> 37A5> FW_PHY_CNTL<1> 28B4<> 28C3< FW_PHY_DATA<0> 28B8<> FW_PHY_DATA<7..0> 37A5> FW_PHY_DATA<1> 28B8<> FW_PHY_DATA<2> 28B8<> FW_PHY_DATA<3> 28A8<> FW_PHY_DATA<4> 28A8<> FW_PHY_DATA<5> 28A8<> FW_PHY_DATA<6> 28A8<> FW_PHY_DATA<7> 28A8<> FW_PHY_LPS 13C3<> 28B8< FW_PHY_LREQ 13C2< 28B8< 37A5> FW_PHY_PD 14C5< 28B8< FW_PHY_PD_INT 14A7< 14C5<> FW_PHY_RESET_L 28A8< FW_PINT 13C3<> 28B4> 37A5> FW_PLL_ADJ 28C7< FW_PORT1_SEL 28B6< FW_PWREN_L 29C6<> FW_PWR_GATE 29D6<> FW_R0 28A5<> FW_R1 28A5<> FW_TESTM 28A7< FW_TPA0N 28B1<> 29C4<> 37D2> FW_TPA0N_CONN 29C3<> FW_TPA0P 28B1<> 29C4<> 37D2>

INT_UFB_IN 8A6< 8B6< 36D1> INT_UFB_IN_NORM 8A4< 36D1> INT_UFB_LONG 8A4< 36D1> INT_UFB_OUT 8A6<> 8A6< 36D1> INT_UFB_OUT_NORM 8A4< 36D1> INT_UFB_OUT_SHORT 8A5< 36D1> INT_DDRCLK2_N_TP 9B6<> INT_DDRCLK2_P_TP 9B6<> INT_DDRCLK5_N_TP 9B6<> INT_DDRCLK5_P_TP 9B6<> INT_ENET_RST_L 14B5<> 27B8<

35C7<> 35B5<> 38C1> 35C4< 38C1> 35C5< 38C1> 35D5< 38C1> 34A7< 34C6< 31D4<> 5A2< 5D1< 5D5< 7B7< 7D8< 8B8< 8C3< 8C8< 8D1< 8D8< 15D8< 16D8< 23B3< 23B3< 34D8< 38D3> 27B4< 27B4< 27B4< 27B3< 27B5<> 37D2> 27B5<> 37D2> 27B5<> 37D2>

NEC_LEFT_USB_PWREN 24B2<> 26B5<> 39D1> NEC_LEGC 26A7< NEC_MAIN_RESET_L 26A7< 26B7< NEC_NANDTESTEN_TP 26A5< NEC_NANDTESTOUT_TP 26A4<> NEC_NC1_TP 26B5<> NEC_NC2_TP 26B5<> NEC_OCI<1> 26B5< 26C3< NEC_OCI<2> 26B5< 26C3< NEC_OCI<3> 26B5< NEC_OCI<4> 26B5< NEC_OCI<5> 26B5< NEC_PCI_INTA_L 26A7< 26B7> NEC_PCI_INTB_L 26A7< 26B7> NEC_PCI_INTC_L 26A7< 26B7> NEC_PCI_PERR_L 26B7<> 26C8< NEC_PCI_SERR_L 26B7> 26C8<

U_DATA<56> U_DATA<57> U_DATA<58> U_DATA<59> U_DATA<60> U_DATA<61> U_DATA<62>

6B8<> 6B8<> 6B8<> 6B8<> 6B8<> 6B8<> 6A8<>

U_DATA<63> U_DBG_L U_DRDY_L U_DRDY_L_UF U_DTI<0> U_DTI<0..2>

6A8<> 8B3< 8B4<> 5C4< 8A4<> 8C2< 36D5> 5C4> 8A4< 8C2< 36D5> 36D5> 5C4< 8A4<> 36D5>

ENET_HSDA 27A7<> ENET_LINK_RXD<0> 13C5< 27C7> ENET_LINK_RXD<7..0> 37A5> ENET_LINK_RXD<1> 13C5< 27C7> ENET_LINK_RXD<2> 13C5< 27C7> ENET_LINK_RXD<3> 13C5< 27B7>

GPU_THERM_DP_TP GPU_TV_GND1 GPU_TV_GND2 GPU_VCORE

AIRPORT_CLKRUN_L 24C6<> 39C1> AIRPORT_IDSEL 24C5<> 39B1> AIRPORT_PCI_GNT_L 12D7<> 24D5<> 39C4> AIRPORT_PCI_INT_L 14B5<> 14D7< 24D5<> 39C4> AIRPORT_PCI_REQ_L 12A7< 12D7<> 24D6<> 39D4> AIRPORT_PME_L_TP 24D5<> AMP_CONTROL 25C5<> 25D5<> ATI_AGP_FBSKEW<0> 19C2< 19C7<> ATI_AGP_FBSKEW<1> 19C2< 19C7<> ATI_BUS_CFG<0> 19B2< 19C7<> ATI_BUS_CFG<1> 19B2< 19C7<> ATI_BUS_CFG<2> 19B2< 19C7<> ATI_CLK27M_IN 18C1< 19B7< ATI_CLK27M_OSC 18D2< ATI_CLK27M_OSC_SS 18B2< 18D1< ATI_DBI_HI_PU 18C6<> ATI_DBI_LO_PU 18C6<> ATI_GPIO7_SPN 19C7<> ATI_GPIO8_PD 19C7<> ATI_GPIO9_SPN 19C7<> ATI_GPIO10_SPN 19C7<> ATI_GPIO11_SPN 19C7<>

CLK18M_INT_XIN CLK18M_INT_XOUT CLK18M_XTAL_IN CLK25M_ENET_XIN CLK25M_ENET_XOUT

14A5< 36B1> 14A5<> 36B1> 14A5< 36B1> 27A7< 36B1> 27A7<> 36B1>

U_DTI<1> U_DTI<2> U_EDTI U_EMODE0_L U_EMODE1_L

5C4< 5C4< 5B2< 5A4< 5A4<

ENET_LINK_RXD<4> ENET_LINK_RXD<5> ENET_LINK_RXD<6> ENET_LINK_RXD<7> ENET_LINK_TXD<0>

CLK25M_XTAL_IN CLK27M_GPU_XIN CLK27M_GPU_XOUT CLK27M_XTAL_IN CLK32K_PMU_XIN CLK32K_PMU_XOUT

27A7< 36B1> 36B1> 36B1> 30B3<> 30B3<>

CLK32K_PMU_XOUT_UF 30B2<> CLK33M_AIRPORT 12D8< 24D5<> 36C1> 39B1> CLK33M_AIRPORT_UF 12C7<> 36C1> CLK33M_CBUS 12D8< 17A7< 36C1> CLK33M_CBUS_UF 12C7<> 36C1>

U_GBL_L U_HIT_L U_HRESET_INV U_HRESET_L U_L1TSTCLK U_L2TSTCLK U_LSSD_MODE U_M_L U_M_DM U_M_DP U_PLL_CFG<0>

5A7<> 8B6<> 36D5> 5A7> 8B6< 8D2< 36D5> 7A7<> 5B4< 5C2< 7A5< 7A8< 23A2<> 39C8> 5B2< 5B4< 5B4< 5C2< 5B4< 5C2< 5B4< 5D2< 25A8< 25B6< 25B6< 25B8< 5C4< 7D3<

CLK33M_USB2 12C8< 26B7< 36C1> CLK33M_USB2_UF 12C7<> 36C1> CLK66M_AGP_15V_TP 12C4> CLK66M_GPU_AGP 12C8< 18B7< 36C1> CLK66M_GPU_AGP_UF 12C7<> 36C1> CLKENET_LINK_GBE_REF 13C5< 27C8< 36B1>

U_PLL_CFG<1> U_PLL_CFG<2> U_PLL_CFG<3> U_PLL_CFG<4> U_PLL_CFGEXT U_PLL_FS00

5C4< 7D3< 5C4< 7D3< 5C4< 7D3< 5C4< 7D3<> 7D4<> 7C4<>

ATI_GPIO12_SPN 19C7<> ATI_GPIO13_SPN 19C7<> ATI_HSYNC 19D5<> 22C8< ATI_MEMTEST 18A6<> ATI_MEMVMODE0 18A7< ATI_MEMVMODE1 18A7< ATI_OSC_OE 18D3< ATI_PVDD_BYP 21D6<> ATI_R2SET 19D6<> ATI_RSET 19D6<> ATI_RSTB_MSK 18C6<> ATI_SSCLK_IN 18B1< 19B7<> ATI_SSCLK_UF 18B1<> ATI_TESTEN 19B7< ATI_TMDS_CLKN 19B7> 20B4< ATI_TMDS_CLKP 19B7> 20B4< ATI_TMDS_DN<0> 19B7> 20B4< ATI_TMDS_DN<1> 19B7> 20A4< ATI_TMDS_DN<2> 19B7> 20A4< ATI_TMDS_DP<0> 19B7> 20B4< ATI_TMDS_DP<1> 19B7> 20A4< ATI_TMDS_DP<2> 19B7> 20A4< ATI_TPVDD_BYP 21D1<> ATI_VSYNC 19D5<> 22C8< ATI_X1CLK_SKEW<0> 19C2< 19C7<> ATI_X1CLK_SKEW<1> 19B2< 19C7<> BATTV_HIGH 31B7<> BATTV_LOW 31B8<> BATT_14PBUS_EN 31C1<> BATT_14V_GATE 31C1<> BATT_24PBUS_EN 31C2<> BATT_24V_GATE 31C1<> BATT_CLK 31A4<> 39C3>

CLKENET_LINK_GTX 13C5<> 36A1> CLKENET_LINK_RX 13D5< 27C8< 36B1> CLKENET_LINK_TX 13D5< 27D8< 36A1> CLKENET_PHY_GBE_REF 27C7<> 36B1> CLKENET_PHY_GTX 13C6< 27C7< 36A1> CLKENET_PHY_RX 27C7<> 36B1> CLKENET_PHY_TX 27D7<> 36B1> CLKFW_LINK_LCLK 13C3<> 36A1> CLKFW_LINK_PCLK 13C3<> 28C3< 36A1> CLKFW_PHY_LCLK 13C2< 28B8< 36A1> CLKFW_PHY_PCLK 28B4> 28C3< 36A1>

BATT_DATA BATT_DIV BATT_LOW BATT_LOW_L BATT_NEG BBANG_HRESET_L BBANG_JTAG_TCK BBANG_TCK_EN BCKFD_PROT_EN_L BCKFD_PROT_GATE BRIGHT_PWM BRIGHT_PWM_UF BT_USB_DM BT_USB_DP CAPSLOCK_LED CAPSLOCK_LED_L CBUS_ADDR<0> CBUS_ADDR<1> CBUS_ADDR<2> CBUS_ADDR<3> CBUS_ADDR<4> CBUS_ADDR<5> CBUS_ADDR<6> CBUS_ADDR<7> CBUS_ADDR<8> CBUS_ADDR<9> CBUS_ADDR<10> CBUS_ADDR<11> CBUS_ADDR<12> CBUS_ADDR<13> CBUS_ADDR<14> CBUS_ADDR<15> CBUS_ADDR<16> CBUS_ADDR<17> CBUS_ADDR<18> CBUS_ADDR<19> CBUS_ADDR<20> CBUS_ADDR<21> CBUS_ADDR<22> CBUS_ADDR<23> CBUS_ADDR<24> CBUS_ADDR<25> CBUS_ADDR_16_UF CBUS_BVD1_L CBUS_BVD2_L CBUS_CE1_L CBUS_CE2_L CBUS_DATA<0> CBUS_DATA<1> CBUS_DATA<2> CBUS_DATA<3> CBUS_DATA<4> CBUS_DATA<5> CBUS_DATA<6> CBUS_DATA<7> CBUS_DATA<8> CBUS_DATA<9> CBUS_DATA<10> CBUS_DATA<11> CBUS_DATA<12> CBUS_DATA<13> CBUS_DATA<14> CBUS_DATA<15> CBUS_DET_1_L CBUS_DET_2_L CBUS_INPACK_L CBUS_INT_L CBUS_IORD_L CBUS_IOWR_L CBUS_MFUNC1_PD CBUS_MFUNC2_PD CBUS_MFUNC3_PD CBUS_MFUNC4_PD CBUS_MFUNC5_PD CBUS_MFUNC6_PD CBUS_OE_L CBUS_PCI_GNT_L CBUS_PCI_IDSEL CBUS_PCI_PERR_L CBUS_PCI_REQ_L CBUS_PCI_RESET_L CBUS_PCI_SERR_L CBUS_READY CBUS_REG_L CBUS_RESET_L CBUS_SUSPEND_PU CBUS_VCCD0_L CBUS_VCCD1_L CBUS_VPPD0 CBUS_VPPD1 CBUS_VS1 CBUS_VS2 CBUS_WAIT_L CBUS_WE_L CBUS_WP_L CG_ADDRSEL CG_CLKOUT CG_FSEL CG_LOCK CG_RESET_L

37C2> 37C2> 37C2> 37C2> 39B2>

39B7> 39B7> 39B7> 39A7>

8A4<> 8A4<> 5C4< 7A4< 5C2<

CLKLVDS_LN CLKLVDS_LP CLKLVDS_UN CLKLVDS_UP COMM_DTR_L

19B5> 19B5> 19B5> 19B5> 14C2>

COMM_GPIO_L COMM_RESET_L COMM_RING_DET_L COMM_RTS_L COMM_RXD COMM_SHUTDOWN COMM_TRXC COMM_TXD_L COMP_DISABLE COMP_ENABLE COMP_RC

14C2<> 25D2<> 39C2> 14C5<> 25C4<> 39C4> 14B5<> 14C7< 25C3<> 30C6<> 39C4> 14C2> 25D1<> 39B2> 14C2<> 25D1<> 39B2> 14C5<> 25C4<> 39C4> 14C2<> 25D2<> 39C2> 14C2<> 25D2<> 39C2> 22C2<> 22C1<> 32C6<

U_TBST_L U_TEA_L U_THERM_DM U_THERM_DP U_TSIZ<0> U_TSIZ<0..2> U_TSIZ<1> U_TSIZ<2> U_TS_L U_TT<0> U_TT<0..4>

U_AACK_L U_ADDR<0> U_ADDR<0..31> U_ADDR<1> U_ADDR<2> U_ADDR<3>

5A7< 8B6<> 8C2< 36D5> 5C7<> 8D6<> 36D5> 5C7<> 8D6<> 5C7<> 8D6<> 5C7<> 8D6<>

31A4<> 39C3> 31A5< 31A6<> 31B6<> 31A4<> 38C6> 39C3> 23A4< 23C4<> 39C1> 23B3< 23C4<> 23B3< 31C6<> 31D6<> 22A1<> 39A7> 22A2<> 14B1< 24B2<> 37B2> 39B6> 14C1< 24B2<> 37B2> 39B6> 23A8< 23B8< 30C7< 17B1<> 17B4> 17B1<> 17B4> 17B1<> 17B4> 17B1<> 17B4> 17B1<> 17B4> 17B1<> 17B4> 17B1<> 17B4> 17B1<> 17B4> 17B1<> 17B4> 17B1<> 17B4> 17B4> 17C1<> 17B1<> 17B4> 17B1<> 17B4> 17B1<> 17B4> 17B1<> 17B4> 17B1<> 17B4> 17B1<> 17B4< 17B2<> 17B4> 17B2<> 17B4> 17B2<> 17B4> 17B2<> 17B4> 17B2<> 17B4> 17A4> 17B2<> 17A4> 17B2<> 17A4> 17B2<> 17A4> 17B2<> 17B5<> 17B2<> 17C4< 17B2<> 17C4< 17C1<> 17C4> 17B4> 17C2<> 17A1<> 17A4<> 17A1<> 17A4<> 17A1<> 17A4<> 17A4<> 17C1<> 17A4<> 17C1<> 17A4<> 17C1<> 17A4<> 17C1<> 17A4<> 17C1<> 17A2<> 17A4<> 17A2<> 17A4<> 17A2<> 17A4<> 17A4<> 17C2<> 17A4<> 17C2<> 17A4<> 17C2<> 17A4<> 17C2<> 17A4<> 17C2<> 17C2<> 17C4< 39B8> 17A2<> 17C4< 39B8> 17B2<> 17B4< 14B5<> 14B7< 17A7<> 17B2<> 17C4> 17B2<> 17C4> 17A7< 17A7<> 17A7< 17A7<> 17A7< 17A7<> 17A7< 17A7<> 17A7< 17A7<> 17A7<> 17A7< 17C1<> 17C4> 12D7<> 17A7< 17B7< 17B7<> 17D7< 12A7< 12D7<> 17A7> 17A7< 17B7> 17D7< 17B1<> 17C4< 17B2<> 17C4> 17B2<> 17C4> 17A7< 17D7< 17C4<> 17C4<> 17C4<> 17C5<> 17B2<> 17C4<> 17B2<> 17C4<> 17B2<> 17B4<

U_ADDR<4> U_ADDR<5> U_ADDR<6> U_ADDR<7> U_ADDR<8> U_ADDR<9> U_ADDR<10> U_ADDR<11> U_ADDR<12> U_ADDR<13> U_ADDR<14>

5C7<> 5C7<> 5C7<> 5C7<> 5C7<> 5C7<> 5B7<> 5B7<> 5B7<> 5B7<> 5B7<>

U_TT<1> 5A7<> 8B6<> U_TT<2> 5A7<> 8B6<> U_TT<3> 5A7<> 8B6<> U_TT<4> 5A7<> 8B6<> U_VCORE_HI_OC 7B8< 30D4<> 34C8< 34D7< U_VCORE_PWR_SEQ 34D8<> U_VCORE_SEQ 34D8< U_VCORE_SEQ_L 34D8< U_VCORE_SLEEP 5C3< 5D8<> 6C6<> 34C1< 34D2< 38D3> 39B2> U_VCORE_SLEEP_F 34C2<> U_VCORE_SNUB 34B3< U_WT_L 5A7> 8B6<> 36C5> CSLOT_ADDR3_SPN 13B7> CSLOT_ADDR4_SPN 13B7> CSLOT_ADDR5_SPN 13B7> CSLOT_ADDR6_SPN 13B7>

U_ADDR<15> U_ADDR<16> U_ADDR<17> U_ADDR<18> U_ADDR<19> U_ADDR<20> U_ADDR<21> U_ADDR<22> U_ADDR<23> U_ADDR<24> U_ADDR<25> U_ADDR<26> U_ADDR<27> U_ADDR<28> U_ADDR<29> U_ADDR<30> U_ADDR<31> U_ARTRY_L U_AVDD U_AVDD_ADJ U_AVDD_PG U_AVDD_VIN U_AVDD_VOUT U_BG_L U_BR_L U_BUS_VSEL U_CHKSTP_OUT_L U_CHKS_L U_CI_L U_CLKOUT_SPN U_CLK_EN U_DATA<0> U_DATA<0..31>

5B7<> 8C6<> 5B7<> 8C6<> 5B7<> 8C6<> 5B7<> 8C6<> 5B7<> 8C6<> 5B7<> 8C6<> 5B7<> 8C6<> 5B7<> 8C6<> 5B7<> 8C6<> 5B7<> 8C6<> 5B7<> 8C6<> 5B7<> 8C6<> 5B7<> 8C6<> 5B7<> 8C6<> 5B7<> 8C6<> 5B7<> 8C6<> 5B7<> 8B6<> 5A7<> 8B6<> 8D2< 36D5> 5C3< 38D3> 5C2<> 5C3<> 5C3< 5C3<> 5C7< 8C2< 8D6<> 36D5> 5C7> 8D2< 8D6< 36D5> 5C4< 7A6< 5B4<> 5C2< 39D8> 5A4< 5D2< 5A7> 8B6<> 36D5> 5C4> 8A6< 30C4<> 6D8<> 8D4<> 36D5>

U_DATA<1> U_DATA<2> U_DATA<3> U_DATA<4> U_DATA<5> U_DATA<6> U_DATA<7> U_DATA<8> U_DATA<9> U_DATA<10> U_DATA<11> U_DATA<12> U_DATA<13> U_DATA<14> U_DATA<15> U_DATA<16> U_DATA<17> U_DATA<18> U_DATA<19> U_DATA<20> U_DATA<21> U_DATA<22>

6D8<> 6D8<> 6D8<> 6D8<> 6D8<> 6D8<> 6D8<> 6D8<> 6D8<> 6C8<> 6C8<> 6C8<> 6C8<> 6C8<> 6C8<> 6C8<> 6C8<> 6C8<> 6C8<> 6C8<> 6C8<> 6C8<>

U_DATA<23> U_DATA<24> U_DATA<25> U_DATA<26> U_DATA<27> U_DATA<28> U_DATA<29> U_DATA<30> U_DATA<31> U_DATA<32> U_DATA<32..63> U_DATA<33> U_DATA<34> U_DATA<35> U_DATA<36> U_DATA<37> U_DATA<38> U_DATA<39> U_DATA<40> U_DATA<41> U_DATA<42> U_DATA<43> U_DATA<44> U_DATA<45> U_DATA<46> U_DATA<47> U_DATA<48>

6C8<> 8C4<> 6C8<> 8C4<> 6C8<> 8C4<> 6C8<> 8C4<> 6C8<> 8C4<> 6C8<> 8C4<> 6C8<> 8C4<> 6C8<> 8C4<> 6C8<> 8C4<> 6C8<> 8C4<> 8D8< 36D5> 6C8<> 8C4<> 8D8< 6C8<> 8C4<> 8D8< 6C8<> 8C4<> 8D8< 6B8<> 8C4<> 8D8< 6B8<> 8C4<> 8D8< 6B8<> 8B4<> 8D8< 6B8<> 8B4<> 8D8< 6B8<> 8B4<> 8C8< 6B8<> 8B4<> 8C8< 6B8<> 8B4<> 8C8< 6B8<> 8B4<> 8C8< 6B8<> 8B4<> 8C8< 6B8<> 8B4<> 8B8< 6B8<> 8B4<> 8B8< 6B8<> 8B4<> 8B8< 6B8<> 8A8< 8B4<>

17B1<> 17C4> 17A1<> 17B4< 14B7< 14B6<> 14B7< 14C5< 14B7<> 14B7<

U_DATA<49> U_DATA<50> U_DATA<51> U_DATA<52> U_DATA<53> U_DATA<54>

6B8<> 6B8<> 6B8<> 6B8<> 6B8<> 6B8<>

U_DATA<55>

6B8<> 8A8< 8B4<>

8D6<> 8C6<> 8C6<> 8C6<> 8C6<> 8C6<> 8C6<> 8C6<> 8C6<> 8C6<> 8C6<>

CSLOT_ADDR7_SPN CSLOT_ADDR8_SPN CSLOT_ADDR9_SPN CSLOT_CE1_L_SPN CSLOT_CE2_L_SPN

13B7> 13B7> 13B7> 13C7> 13C7>

CSLOT_IORD_L_SPN 13C7> CSLOT_IOWAIT_L_PU 13C7< CSLOT_IOWR_L_SPN 13C7> CSLOT_OE_L_SPN 13C7> CSLOT_WE_L_SPN 13C7> CURRENT_THRESHOLD 31C4< CY25811_S0 18B2< CY25811_S1 18B2< DCDC_EN 19A7<> 29C7<> 33B7<> 34C8<> 39C1> DCDC_EN_L 33B6< 33B7<> 35C7<> DDC_CLK_ISO 22D4<> DDR_VREF 11D1< 11D3<> 11D5<> 11D6<> 11D8<> 38D3> DVI_DDC_CLK 22D4<> DVI_DDC_CLK_UF 22C5<> 22D3<> 39C7> DVI_DDC_DATA 22C4<> DVI_DDC_DATA_UF 22C5<> 39C7> DVI_HPD 22C4<> DVI_HPD_DIV 22C3< DVI_HPD_UF 22C3< 22C5<> 39C7> DVI_TRUN_ON_ILIM 22D2< DVI_TURN_ON 22D3<> DVI_TURN_ON_BASE 22D2< EEPROM_ADDR 23D4< EEPROM_WP_PD 23D3<> EIDE_ADDR<0> 13B7> 24B8< EIDE_ADDR<2..0> 37B5> EIDE_ADDR<1> 13B7> 24B8< EIDE_ADDR<2> 13B7> 24B8< EIDE_CS0_L 13B7> 24B8< 37B5> EIDE_CS1_L 13B7> 24B8< 37B5> EIDE_DATA<0> 13C7<> 24C8< EIDE_DATA<15..0> 37B5> EIDE_DATA<1> 13C7<> 24C8< EIDE_DATA<2> 13C7<> 24C8< EIDE_DATA<3> 13C7<> 24C8< EIDE_DATA<4> 13C7<> 24C8< EIDE_DATA<5> 13B7<> 24B8< EIDE_DATA<6> 13B7<> 24C8< EIDE_DATA<7> 13B7<> 24C8< EIDE_DATA<8> 13B7<> 24D8< EIDE_DATA<9> 13B7<> 24D8< EIDE_DATA<10> 13B7<> 24D8< EIDE_DATA<11> 13B7<> 24D8< EIDE_DATA<12> 13B7<> 24D8< EIDE_DATA<13> 13B7<> 24C8< EIDE_DATA<14> 13B7<> 24C8< EIDE_DATA<15> 13B7<> 24C8< EIDE_DMACK_L 13A7<> 24A8< 37B5> EIDE_DMARQ 13A7< 24B8< 37B5>

8D4<> 8D4<> 8D4<> 8D4<> 8D4<> 8D4<> 8D4<> 8D4<> 8D4<> 8D4<> 8D4<> 8C4<> 8C4<> 8C4<> 8C4<> 8C4<> 8C4<> 8C4<> 8C4<> 8C4<> 8C4<> 8C4<>

8A8< 8A8< 8A8< 8A8< 8A8< 8A8<

5C2< 30C4<> 5B4< 39C8> 5C2< 8A4<> 8D2< 36D5> 5D2< 8A6<>

EIDE_INT 13A7< 24A8< 37B5> EIDE_IOCHRDY 13B7< 24A8< 37B5> EIDE_OPTICAL_ADDR<0> 24A5<> 24B7< 39A4> EIDE_OPTICAL_ADDR<2..0> 37B5> EIDE_OPTICAL_ADDR<1> 24A5<> 24B7< 39A4> EIDE_OPTICAL_ADDR<2> 24A6<> 24B7< 39A4> EIDE_OPTICAL_CS0_L 24A5<> 24B7< 37B5> 39D4> EIDE_OPTICAL_CS1_L 24A6<> 24B7< 37B5> 39D4> EIDE_OPTICAL_DATA<0> 24A5<> 24C7< 39C4> EIDE_OPTICAL_DATA<15..0> 37B5> EIDE_OPTICAL_DATA<1> 24A5<> 24C7< 39C4> EIDE_OPTICAL_DATA<2> 24A5<> 24C7< 39C4> EIDE_OPTICAL_DATA<3> 24A5<> 24C7< 39C4> EIDE_OPTICAL_DATA<4> 24A5<> 24C7< 39C4> EIDE_OPTICAL_DATA<5> 24A5<> 24B7< 39C4> EIDE_OPTICAL_DATA<6> 24A5<> 24C7< 39C4> EIDE_OPTICAL_DATA<7> 24A5<> 24C7< 39B4> EIDE_OPTICAL_DATA<8> 24A6<> 24D7< 39B4> EIDE_OPTICAL_DATA<9> 24A6<> 24D7< 39B4> EIDE_OPTICAL_DATA<10> 24A6<> 24D7< 39B4> EIDE_OPTICAL_DATA<11> 24A6<> 24D7< 39B4> EIDE_OPTICAL_DATA<12> 24A6<> 24D7< 39B4> EIDE_OPTICAL_DATA<13> 24A6<> 24C7< 39B4> EIDE_OPTICAL_DATA<14> 24A6<> 24C7< 39B4> EIDE_OPTICAL_DATA<15> 24A6<> 24C7< 39B4> EIDE_OPTICAL_DMAACK_L 24A6<> 24A7< 37A5> 39A4> EIDE_OPTICAL_DMA_RQ 24A6<> 24B7< 37A5> 39A4> EIDE_OPTICAL_INT 24A5<> 24A7< 37A5> 39D4> EIDE_OPTICAL_IOCHRDY 24A5<> 24A7< 37A5> 39D4> EIDE_OPTICAL_RD_L 24A6<> 24A7< 37B5> 39A4> EIDE_OPTICAL_RST_L 24A7< 24B5<> 37A5> 39D4> EIDE_OPTICAL_WR_L 24A5<> 24A7< 37A5> 39D4> EIDE_RD_L 13A7> 24A8< 37B5>

8B4<> 8B4<> 8B4<> 8B4<> 8B4<> 8B4<>

EIDE_RST_L

13B7> 24A8< 37B5>

13C5< 13C5< 13C5< 13C5< 13B4<

27B7> 27B7> 27B7> 27B7> 13D5>

13B5< 27C7< 13B5< 27C7< 13A5< 27C7< 13A5< 27C7< 13D6< 27C7< 13D6< 27C7< 27A5< 27B7< 13D5< 27B7> 13C5< 27B7> 27A7<>

37A5> 37A5>

37A5> 37A5>

18A6<> 22B8<> 38B6> 22A8<> 38B6> 18A6< 19A3<> 19B5<> 19D4< 38C3> 39B2> GPU_VCORE_CNTL 19A3<>

MAX1715_FB2 MAX1715_GND

INT_AGPPVT 12D4<> INT_AGP_FB_IN 12C4< 36C1> INT_AGP_FB_OUT 12C4<> 36C1> INT_AGP_VREF 12B4< 12D4<> 18D5< 38D3> INT_AUDIO_TO_SND 14B2< 25D8< 39C6> INT_AUDIO_TO_SND_F 25D7<> 25D7<

MAX1715_ON_RC MAX1715_REF MAX1715_SKIP MAX1715_TON MAX1715_VCC MAX1717_AB_SEL MAX4172_OUT MAXBUS_SLEEP

MDI0_PD MDI1_PD MDI2_PD MDI3_PD MDI_M<0> MDI_M<1> MDI_M<2>

INT_EXTINT3_PU INT_EXTINT8_PU INT_EXTINT10_PU INT_EXTINT11_PU INT_EXTINT12_PU INT_EXTINT13_PU INT_EXTINT14_PU INT_EXTINT16_PU INT_GPIO0 INT_GPIO1_PU INT_GPIO9_PU INT_GPIO12_PU INT_GPIO15_PU INT_I2C_CLK0

FW_TPA0P_CONN FW_TPA1N FW_TPA1P FW_TPB0N FW_TPB0N_CONN FW_TPB0P FW_TPB0P_CONN FW_TPB1N FW_TPB1P FW_TPB2_PD FW_TPI0N FW_TPI0P FW_TPI1N FW_TPI1P FW_TPO0N FW_TPO0P FW_TPO0R FW_TPO1N FW_TPO1P FW_VGND0 FW_VGND1 FW_VREG_PD FW_XI GAIN_SETTING2 GPU_AGP_TEST GPU_AUXWIN GPU_B GPU_C GPU_CLK27M_OUT GPU_CLK27M_UF GPU_COMP GPU_CORE_OK GPU_DVI_DDC_CLK GPU_DVI_DDC_DATA GPU_DVOD<0> GPU_DVOD<0..11> GPU_DVOD<1> GPU_DVOD<2> GPU_DVOD<3> GPU_DVOD<4> GPU_DVOD<5> GPU_DVOD<6> GPU_DVOD<7> GPU_DVOD<8> GPU_DVOD<9> GPU_DVOD<10> GPU_DVOD<11> GPU_DVOD_DE GPU_DVO_CLKP

29C3<> 28B1<> 29A4<> 37C2> 28B1<> 29A4<> 37C2> 28B1<> 29C4<> 37D2> 29C3<> 28B1<> 29C4<> 37D2> 29C3<> 28B1<> 29A4<> 37C2> 28B1<> 29A4<> 37C2> 28A5<> 37C2> 37C2> 29A3<> 37C2> 39D2> 29A3<> 37C2> 39D2> 37C2> 37C2> 29C2<> 38A3> 39A3> 29A3<> 37C2> 39D2> 29A3<> 37C2> 39D2> 29C2<> 38A3> 29A3<> 38A3> 28A7< 28A5<> 36A1> 23C7<> 18D6< 19C5<> 19D6<> 22D8< 19D6<> 22A8< 36C1> 36C1> 19C6<> 22A8< 19A6<> 19D4<> 21D2<> 21D7<> 19C5<> 22D3<> 19C5<> 22C3<> 19D7<> 20B7< 37D5> 19D7<> 20B7< 19D7<> 20B7< 19D7<> 20B7< 19D7<> 20B7< 19D7<> 20A7< 19D7<> 20A7< 19D7<> 20A7< 19D7<> 20A7< 19D7<> 20A7< 19D7<> 20A7< 19D7<> 20A7< 19C7<> 20A7< 19C7<> 20A7< 36B1>

14B5<> 14B7< 14B5<> 14C7< 14A7< 14B5<> 14A7< 14B5<> 14A7< 14B5<> 14B5<> 14B7< 14B5<> 14C7< 14B5<> 14B7< 14C5<> 14C5<> 14C7< 34C8< 14A7< 14B5<> 14B5<> 14B7< 14B5<> 14C7< 11A3<> 11A8<> 13C2< 13C3<> 23D2< 23D4<> 39B8> INT_I2C_CLK1 13C2< 13C3<> 14B7< 25B4< 39B8> INT_I2C_CLK2 14A2<> 25C4<> 25D7<> 39C6> INT_I2C_DATA0 11A3<> 11A8<> 13C2< 13C3<> 23D2<> 23D4<> 39B8> INT_I2C_DATA1 13B2< 13C3<> 14B7< 25B4<> 39B8> INT_I2C_DATA2 14A2<> 25C4<> 25C7<> 39C6> INT_JTAG_TEI 13C2< 13C5< INT_MEM_REF_H 9B6< 38D3> INT_MEM_VREF 9A7< 9B6<> 38D3> INT_MOD_BITCLK_UF 14A3<> 14A7< INT_MOD_CLKOUT_UF 14A3<> 14B7< INT_MOD_DTI 14A2< 25C3<> 39B1> INT_MOD_DTI_UF 14A7< INT_MOD_DTO_UF 14A3<> 14B7< INT_MOD_SYNC_UF 14A3<> 14A7< INT_PCI_FB_IN 12C7< 36C1> INT_PCI_FB_OUT 12C7<> 36C1> INT_PEND_PROC_INT 14A5> 30C4<> INT_PROC_SLEEP_REQ_L 14A5< 30B4<> INT_PU_RESET_L 13D3< 25D4<> 30A2< 30C4<> INT_REF_CLK_IN 14A5< 14B5< 36C1> INT_REF_CLK_OUT 14A5> 14B7< 36C1> INT_RESET_L 9B3< 13D3< 30C7< 30D4<> INT_ROM_CS_L 12A6< 12C7> INT_ROM_OE_L 12A6< 12C7> INT_ROM_RW_L 12A6< 12C7> INT_SND_CLKOUT 14A3<> INT_SND_SCLK 14A3<> INT_SND_SYNC 14B3<> INT_SND_TO_AUDIO 14B3<> INT_SUSPEND_ACK_L 8B6> 30B6<> INT_SUSPEND_REQ_L 8B6< 30B6<> 30C7< INT_TST_MONIN_PD 13C2< 13C5< INT_TST_MONOUT_TP 13C5> INT_TST_PLLEN_PD 13C5< 13D2< INT_WATCHDOG_L 14A5> 30C6<> INV_ON_PWM 19C6<> 22A3< IO_RESET_L 17A7< 23D6< 26B8< 27B8< 30C6<> 30D7< JTAG_ASIC_TCK 13C5< 13D2< 27A5< 39D8> JTAG_ASIC_TDI 27A5< 27D7< 39D8> JTAG_ASIC_TDO 13C5> 13D2< 14A7< 39D8> JTAG_ASIC_TMS 13C5< 13D2< 27A5< 39D8> JTAG_ASIC_TRST_L 13C2< 13C5< 27A5< 39D8> JTAG_U_TCK 5B2< 5B4< 23B2> 39C8> JTAG_U_TDI 5B2< 5C4< 23D4<> 39C8> JTAG_U_TDO_TP 5C4> 39C8> JTAG_U_TMS 5B2< 5B4< 23C4<> 39C8> JTAG_U_TRST_L 5A3< 5B4< 23D4<> 39B1> 39C8> JTAG_ENET_TDO 13C5< 13D2< 27A5> KBD_CAPSLOCK_LED 23A7<> 39B4> KBD_COMMAND_L 23A5< 23A7<> 30C6<> 39B4> KBD_CONTROL_L 23A5< 23A7<> 30A8< 30C6<> 39B4> KBD_FUNCTION_L 23A5< 23A7<> 30B6<> 39B4> KBD_ID 23A7<> 23B5< 30B6<> 39C4> KBD_LED1_OUT 23A5<> 23A7<> 38B6> 39C2> KBD_LED2_OUT 23A5<> 23A7<> 38B6> 39C2> KBD_LED_EN 23A5<> KBD_LED_SET 23A5< KBD_NUMLOCK_LED 23B7<> 39C3> KBD_OPTION_L 23A5< 23B7<> 30A8< 30B6<> 39B4> KBD_SHIFT_L 23A5< 23B7<> 30A8< 30C6<> 39B4> KBD_X<0> 23A5< 23B7<> 30C6<> 39B4> KBD_X<1> 23A5< 23B7<> 30C6<> 39B4> KBD_X<2> 23B5< 23B7<> 30C6<> 39B4> KBD_X<3> 23B5< 23B7<> 30C6<> 39A4> KBD_X<4> 23B5< 23B7<> 30C6<> 39A4>

GPU_DVO_HSYNC GPU_DVO_VSYNC GPU_FBCLK0 GPU_FBCLK0_L GPU_FBCLK1 GPU_FBCLK1_L

19C7<> 20A7< 37C5> 19C7<> 20A7< 37C5> 36B1> 36B1> 36B1> 36B1>

KBD_X<5> KBD_X<6> KBD_X<7> KBD_X<8> KBD_X<9> KBD_Y<0>

23B5< 23B7<> 30C6<> 23B5< 23B7<> 30C6<> 23B5< 23B7<> 30C6<> 23B5< 23B7<> 30C6<> 23B5< 23B7<> 30C6<> 23B7<> 30D6<> 39D3>

GPU_G

19D6<> 22D8<

KBD_Y<1>

23B7<> 30D6<> 39D3>

39A4> 39A4> 39A4> 39A4> 39D3>

30D6<> 30D6<> 30D6<> 30D6<> 30C6<> 30C6<>

1 MEM_DATA<51> MEM_DATA<52> MEM_DATA<53> MEM_DATA<54> MEM_DATA<55> MEM_DATA<56> MEM_DATA<63..56> MEM_DATA<57> MEM_DATA<58> MEM_DATA<59> MEM_DATA<60> MEM_DATA<61> MEM_DATA<62>

CHARGE_LED_L 30C6<> 30D7< 31D8<> 39D2> CHGND1 38A6> CHGND2 38A6> CHGND3 38A6> CHGND4 38A6> 39B6> CHGND5 38A6> CHGND6 38A6> CLK10M_PMU_XIN 30B6< CLK10M_PMU_XOUT 30B6< CLK10M_PMU_XOUT_UF 30B7< CLK18M_INT_EXT 14A6<> 36B1>

22A4<> 22A4<> 22A4<> 22A4<> 25D1<>

8B4<> 8B4<> 8B4<> 8B4<> 8B4<> 8B4<> 8B4<>

13A7> 24A8< 37B5> 13C5< 27B7> 37A5> 27B7<> 13C5< 27B7> 37A5> 27A1< 38A6> 14B5<> 27B7<> 27A7<>

GPU_HPD GPU_MEM_IO

KBD_Y<2> KBD_Y<3> KBD_Y<4> KBD_Y<5> KBD_Y<6> KBD_Y<7> LCD_DIGON_L LCD_PWREN_L LED_LINK10 LED_LINK100 LED_RX_SPN LEFT_USB_DM LEFT_USB_DP

8B3< 8B3< 8B3< 8B3< 8B3< 8B3< 8B3<

EIDE_WR_L ENET_COL ENET_COMA ENET_CRS ENET_CTAP_CHGND ENET_ENERGY_DET ENET_HSDACM

2

3

4

5

39D3> 39D3> 39D3> 39D3> 39C3> 39C3>

26B3< 37A2> 39D1> 26A3< 37A2> 39D1>

10B3<> 10C1<> 10B1<> 10C7<> 10B7<> 10C5<>

D 36B5> 36A5> 36C5> 36C5>

10B5<>

10B3<> 10C1<> 36B5> 10B1<> 36A5> 10A6<

MDI_M<3> MDI_P<0> MDI_P<1> MDI_P<2> MDI_P<3> MEM_ADDR<0> MEM_ADDR<12..0> MEM_ADDR<1> MEM_ADDR<2> MEM_ADDR<3> MEM_ADDR<4> MEM_ADDR<5> MEM_ADDR<6> MEM_ADDR<7> MEM_ADDR<8> MEM_ADDR<9> MEM_ADDR<10> MEM_ADDR<11> MEM_ADDR<12> MEM_BA<0> MEM_BA<1..0> MEM_BA<1> MEM_CAS_L MEM_CKE<0> MEM_CKE<3..0> MEM_CKE<1> MEM_CKE<2> MEM_CKE<3> MEM_CS_L<0> MEM_CS_L<3..0> MEM_CS_L<1> MEM_CS_L<2> MEM_CS_L<3> MEM_DATA<0> MEM_DATA<7..0> MEM_DATA<1> MEM_DATA<2> MEM_DATA<3> MEM_DATA<4> MEM_DATA<5> MEM_DATA<6> MEM_DATA<7> MEM_DATA<8> MEM_DATA<15..8> MEM_DATA<9> MEM_DATA<10> MEM_DATA<11> MEM_DATA<12> MEM_DATA<13> MEM_DATA<14> MEM_DATA<15> MEM_DATA<16> MEM_DATA<31..16> MEM_DATA<17> MEM_DATA<18>

27B5<> 37D2> 27B5<> 37D2> 27B5<> 37D2> 27B5<> 37D2> 27B5<> 37D2> 9B5< 9D6<> 36A5> 9B5< 9D6<> 9B5< 9D6<> 9B5< 9D6<> 9B5< 9D6<> 9B5< 9D6<> 9B5< 9D6<> 9B5< 9D6<> 9B5< 9D6<> 9A5< 9D6<> 9A5< 9D6<> 9A5< 9D6<> 9A5< 9D6<> 9A5< 9D6<> 36A5> 9A5< 9C6<> 9A5< 9C6<> 36A5> 9B6<> 9C5< 36A5> 9B6<> 9C5< 9B6<> 9C5< 9B6<> 9C5< 9C5< 9C6<> 36A5> 9C5< 9C6<> 9C5< 9C6<> 9C5< 9C6<> 9D8<> 10C7<> 36C5> 9D8<> 10C7<> 9D8<> 10C7<> 9D8<> 10C7<> 9D8<> 10C7<> 9D8<> 10C7<> 9D8<> 10C7<> 9D8<> 10C7<> 9D8<> 10C7<> 36C5> 9D8<> 10C7<> 9D8<> 10C7<> 9D8<> 10C7<> 9D8<> 10B7<> 9C8<> 10B7<> 9C8<> 10B7<> 9C8<> 10B7<> 9C8<> 10C5<> 36C5> 9C8<> 10C5<> 9C8<> 10C5<>

NEC_PME_L 26A7> 26B7< NEC_PPON3_TP 26B5> NEC_PPON4_TP 26B5> NEC_PPON5_TP 26B5> NEC_RIGHT_USB_OVERCURRENT 26C1< 32B7<> 39C1> NEC_RIGHT_USB_PWREN 26B5<> 32A7<> 39C1> NEC_RREF 26B5<> NEC_SMI_L_TP 26A7> NEC_USB_DAM 26B4< 26C3<> 37B2> NEC_USB_DAP 26A4< 26C4<> 37B2> NEC_USB_DBM 26A4< 26C3<> 37B2> NEC_USB_DBP 26A4< 26C3<> 37B2> NEC_USB_RSDM1 26C5<> 37B2> NEC_USB_RSDM2 26C5<> 37B2> NEC_USB_RSDP1 26C5<> 37B2> NEC_USB_RSDP2 26C5<> 37B2> NEC_XT1 26D5< 36B1> NEC_XT2 26D5<> 36B1> NEC_XT2_R 26D4< NTEST1_TP 26B5< NUMLOCK_LED 23B8< NUMLOCK_LED_L 23B8< 30C7< OVER_18V_ADJ 31C3<> PCI1510_VR_EN_L 17C7< PCI_AD<0> 9C3< 12D6<> 17C7<> 24B5<> 26D7<> 39B6> PCI_AD<31..0> 37C5> PCI_AD<1> 9C3< 12D6<> 17C7<> 24B6<> 26D7<> 39A6> PCI_AD<2> 9C3< 12D6<> 17C7<> 24C5<> 26D7<> 39A6> PCI_AD<3> 9C3< 12D6<> 17C7<> 24C6<> 26C7<> 39A6>

MEM_DATA<19> MEM_DATA<20> MEM_DATA<21> MEM_DATA<22> MEM_DATA<23> MEM_DATA<24> MEM_DATA<25> MEM_DATA<26> MEM_DATA<27> MEM_DATA<28> MEM_DATA<29> MEM_DATA<30> MEM_DATA<31> MEM_DATA<32> MEM_DATA<47..32> MEM_DATA<33> MEM_DATA<34> MEM_DATA<35> MEM_DATA<36> MEM_DATA<37> MEM_DATA<38> MEM_DATA<39> MEM_DATA<40> MEM_DATA<41> MEM_DATA<42> MEM_DATA<43> MEM_DATA<44>

9C8<> 10C5<> 9C8<> 10C5<> 9C8<> 10C5<> 9C8<> 10C5<> 9C8<> 10C5<> 9C8<> 10C5<> 9C8<> 10C5<> 9C8<> 10C5<> 9C8<> 10C5<> 9C8<> 10C5<> 9C8<> 10B5<> 9C8<> 10B5<> 9C8<> 10B5<> 9C8<> 10C3<> 36B5> 9C8<> 10C3<> 9C8<> 10C3<> 9C8<> 10C3<> 9C8<> 10C3<> 9C8<> 10C3<> 9C8<> 10C3<> 9B8<> 10C3<> 9B8<> 10C3<> 9B8<> 10C3<> 9B8<> 10C3<> 9B8<> 10C3<> 9B8<> 10C3<>

PCI_AD<15>

MEM_DATA<45> MEM_DATA<46> MEM_DATA<47> MEM_DATA<48> MEM_DATA<55..48> MEM_DATA<49>

9B8<> 10B3<> 9B8<> 10B3<> 9B8<> 10B3<> 9B8<> 10C1<> 36B5> 9B8<> 10C1<>

PCI_AD<30>

MEM_DATA<50>

9B8<> 10C1<>

PCI_AD<4> PCI_AD<5> PCI_AD<6> PCI_AD<7> PCI_AD<8> PCI_AD<9> PCI_AD<10> PCI_AD<11> PCI_AD<12> PCI_AD<13> PCI_AD<14>

PCI_AD<16> PCI_AD<17> PCI_AD<18> PCI_AD<19> PCI_AD<20> PCI_AD<21> PCI_AD<22> PCI_AD<23> PCI_AD<24> PCI_AD<25> PCI_AD<26> PCI_AD<27> PCI_AD<28> PCI_AD<29>

PCI_AD<31> PCI_CBE<0> PCI_CBE<3..0> PCI_CBE<1>

9C3< 12D6<> 17C7<> 24C5<> 26C7<> 39A6> 9C3< 12D6<> 17C7<> 24C6<> 26C7<> 39A6> 9C3< 12C6<> 17C7<> 24C5<> 26C7<> 39A6> 9C3< 12C6<> 17C7<> 24C6<> 26C7<> 39D5> 9C3< 12C6<> 17C7<> 24C6<> 26C7<> 39D5> 9C3< 12C6<> 17C7<> 24C5<> 26C7<> 39D5> 9C3< 12C6<> 17C7<> 24C6<> 26C7<> 39D5> 9C3< 12C6<> 17C7<> 24C5<> 26C7<> 39D5> 9C3< 12C6<> 17C7<> 24C6<> 26C7<> 39D5> 9C3< 12C6<> 17C7<> 24C5<> 26C7<> 39C5> 9C3< 12C6<> 17C7<> 24C6<> 26C7<> 39C5> 9C3< 12C6<> 17C7<> 24C5<> 26C7<> 39C5> 9C3< 12C6<> 17C7<> 24C5<> 26C7<> 39C5> 9C3< 12C6<> 17C7<> 24C6<> 26C7<> 39C5> 9C3< 12C6<> 17B7<> 24C5<> 24D4< 26C7<> 39C5> 9C3< 12C6<> 17B7<> 24C6<> 26C7<> 39C5> 9B3< 12C6<> 17B7<> 24C5<> 26C7<> 39C5> 12C6<> 17B7<> 24C6<> 26C7<> 39C5> 12C6<> 17B7<> 24C5<> 26C7<> 39B5> 12C6<> 17B7<> 24C6<> 26C7<> 39B5> 9C1<> 12C6<> 17B7<> 24C5<> 26C7<> 39B5> 9C1<> 12C6<> 17B7<> 24C6<> 26C7<> 39B5> 9C1<> 12C6<> 17B7<> 24C5<> 26C7<> 39B5> 9C1<> 12C6<> 17B7<> 24D6<> 26C8<> 39B5> 9C1<> 12C6<> 17B7<> 24C5<> 26C7<> 39B5> 9C1<> 12C6<> 17B7<> 24D6<> 26B7<> 39B5> 9C1<> 12C6<> 17B7<> 24D5<> 26B7<> 39B5> 9C1<> 12C6<> 17B7<> 24D6<> 26B7<> 39A5> 12C7<> 17B7<> 24C5<> 26B7<> 39D4> 37C5> 12C7<> 17B7<> 24C6<> 26B7<> 39D4>

41

8

7

6

5

4

3

2

1

C

B

A

8 PCI_CBE<2> PCI_CBE<3> PCI_DEVSEL_L PCI_FRAME_L PCI_IRDY_L PCI_PAR PCI_STOP_L PCI_TRDY_L

D

C

B

A

12C7<> 17B7<> 24C6<> 26B7<> 39D4> 12C7<> 17B7<> 24C6<> 26B7<> 39D4> 12B7< 12C7<> 17A7<> 24C5<> 26B7<> 37C5> 39A5> 12B7< 12C7<> 17B7<> 24C5<> 26B7<> 37C5> 39A5> 12B7< 12C7<> 17B7<> 24C6<> 26B7<> 37C5> 39A5> 12C7<> 17B7<> 24C5<> 26B7<> 37C5> 39D4> 12A7< 12C7<> 17B7<> 24C5<> 26B7<> 37C5> 39A5> 12B7< 12C7<> 17A7<> 24C5<> 26B7<>

RAM_DATA_B<12> 10C8<> 11D5<> RAM_DATA_B<13> 10C8<> 11D5<> RAM_DATA_B<14> 10C8<> 11D5<> RAM_DATA_B<15> 10C8<> 11D5<> RAM_DATA_B<16> 10C6<> 11D3<> RAM_DATA_B<31..16> 36B5> RAM_DATA_B<17> 10C6<> 11C3<> RAM_DATA_B<18> RAM_DATA_B<19> RAM_DATA_B<20> RAM_DATA_B<21> RAM_DATA_B<22> RAM_DATA_B<23>

10C6<> 10C6<> 10C6<> 10C6<> 10C6<> 10C6<>

RAM_DATA_B<24> 10C6<> 11C3<> RAM_DATA_B<25> 10C6<> 11C3<> RAM_DATA_B<26> 10C6<> 11C3<> RAM_DATA_B<27> 10C6<> 11C3<> RAM_DATA_B<28> 10C6<> 11C5<> RAM_DATA_B<29> 10C6<> 11C5<> RAM_DATA_B<30> 10C6<> 11C5<> RAM_DATA_B<31> 10C6<> 11C5<> RAM_DATA_B<32> 10D4<> 11B3<> RAM_DATA_B<47..32> 36B5> RAM_DATA_B<33> 10C4<> 11B3<> RAM_DATA_B<34> 10C4<> 11B3<> RAM_DATA_B<35> 10C4<> 11B3<> RAM_DATA_B<36> 10C4<> 11B5<> RAM_DATA_B<37> 10C4<> 11B5<> RAM_DATA_B<38> 10C4<> 11B5<>

PMU_KB_RESET_IN2 30A7<> PMU_KB_RESET_L 30A6> 30B7< 39B2> PMU_LID_CLOSED_L 23A8< 23C4<> 30B2< 30C4<> PMU_NMI_BUTTON_L 25C1< 30C2< 30C4<> PMU_NMI_L 30C2< 30C4<>

RAM_DATA_B<45> 10C4<> 11B5<> RAM_DATA_B<46> 10C4<> 11A5<> RAM_DATA_B<47> 10C4<> 11A5<> RAM_DATA_B<48> 10D2<> 11A3<> RAM_DATA_B<55..48> 36B5> RAM_DATA_B<49> 10C2<> 11A3<> RAM_DATA_B<50> 10C2<> 11A3<> RAM_DATA_B<51> 10C2<> 11A3<> RAM_DATA_B<52> 10C2<> 11A5<> RAM_DATA_B<53> 10C2<> 11A5<> RAM_DATA_B<54> 10C2<> 11A5<>

RAM_ADDR<11> RAM_ADDR<12> RAM_BA<0> RAM_BA<1..0> RAM_BA<1> RAM_CAS_L RAM_CKE<0> RAM_CKE<3..0> RAM_CKE<1> RAM_CKE<2> RAM_CKE<3>

9A4< 11B5<> 11B6<> 9A4< 11B3<> 11B8<> 9A4< 11B3<> 11B8<> 36A5> 9A4< 11B5<> 11B6<> 9A4< 11B5<> 11B6<> 36A5> 9A3< 9C4< 11B6<> 36A5> 9A3< 9C4< 11B8<> 9A3< 9C4< 11C5<> 9A3< 9C4< 11C3<>

RAM_CS_L<0> RAM_CS_L<3..0> RAM_CS_L<1> RAM_CS_L<2> RAM_CS_L<3>

9C4< 11B8<> 36A5> 9C4< 11B6<> 9C4< 11B3<> 9C4< 11B5<>

RAM_DATA_A<0> 10C8<> 11D8<> RAM_DATA_A<7..0> 36C5> RAM_DATA_A<1> 10C8<> 11D8<> RAM_DATA_A<2> 10C8<> 11D8<> RAM_DATA_A<3> 10B8<> 11D8<> RAM_DATA_A<4> 10B8<> 11D6<> RAM_DATA_A<5> 10B8<> 11D6<> RAM_DATA_A<6> 10B8<> 11D6<> RAM_DATA_A<7> 10B8<> 11D6<> RAM_DATA_A<8> 10B8<> 11D8<> RAM_DATA_A<15..8> 36C5> RAM_DATA_A<9> 10C7<> 11D8<> RAM_DATA_A<10> 10C7<> 11D8<> RAM_DATA_A<11> 10C7<> 11D8<> RAM_DATA_A<12> 10C7<> 11D6<> RAM_DATA_A<13> 10C7<> 11D6<> RAM_DATA_A<14> 10C7<> 11D6<> RAM_DATA_A<15> 10C7<> 11D6<> RAM_DATA_A<16> 10C6<> 11D8<> RAM_DATA_A<31..16> 36B5> RAM_DATA_A<17> 10C6<> 11C8<> RAM_DATA_A<18> 10C6<> 11C8<> RAM_DATA_A<19> 10B6<> 11C8<> RAM_DATA_A<20> 10B6<> 11D6<> RAM_DATA_A<21> 10B6<> 11C6<> RAM_DATA_A<22> 10B6<> 11C6<> RAM_DATA_A<23> 10B6<> 11C6<> RAM_DATA_A<24> 10B6<> 11C8<> RAM_DATA_A<25> 10C5<> 11C8<> RAM_DATA_A<26> 10C5<> 11C8<> RAM_DATA_A<27> 10C5<> 11C8<> RAM_DATA_A<28> 10C5<> 11C6<> RAM_DATA_A<29> 10C5<> 11C6<> RAM_DATA_A<30> 10C5<> 11C6<> RAM_DATA_A<31> 10C5<> 11C6<> RAM_DATA_A<32> 10C4<> 11B8<> RAM_DATA_A<47..32> 36B5> RAM_DATA_A<33> 10C4<> 11B8<> RAM_DATA_A<34> 10C4<> 11B8<> RAM_DATA_A<35> 10C4<> 11B8<> RAM_DATA_A<36> 10B4<> 11B6<> RAM_DATA_A<37> 10B4<> 11B6<> RAM_DATA_A<38> 10B4<> 11B6<> RAM_DATA_A<39> 10B4<> 11B6<> RAM_DATA_A<40> 10B4<> 11B8<> RAM_DATA_A<41> 10D3<> 11B8<> RAM_DATA_A<42> 10C3<> 11A8<> RAM_DATA_A<43> 10C3<> 11A8<> RAM_DATA_A<44> 10C3<> 11B6<> RAM_DATA_A<45> 10C3<> 11B6<> RAM_DATA_A<46> 10C3<> 11A6<> RAM_DATA_A<47> 10C3<> 11A6<> RAM_DATA_A<48> 10C2<> 11A8<> RAM_DATA_A<55..48> 36B5> RAM_DATA_A<49> 10C2<> 11A8<> RAM_DATA_A<50> 10C2<> 11A8<> RAM_DATA_A<51> 10C2<> 11A8<> RAM_DATA_A<52> 10B2<> 11A6<> RAM_DATA_A<53> 10B2<> 11A6<> RAM_DATA_A<54> 10B2<> 11A6<> RAM_DATA_A<55> 10B2<> 11A6<> RAM_DATA_A<56> 10B2<> 11A8<> RAM_DATA_A<63..56> 36A5> RAM_DATA_A<57> 10D1<> 11A8<> RAM_DATA_A<58> 10C1<> 11A8<> RAM_DATA_A<59> 10C1<> 11A8<> RAM_DATA_A<60> 10C1<> 11A6<> RAM_DATA_A<61> 10C1<> 11A6<> RAM_DATA_A<62> 10C1<> 11A6<> RAM_DATA_A<63> 10C1<> 11A6<> RAM_DATA_B<0> 10C8<> 11D3<> RAM_DATA_B<7..0> 36C5> RAM_DATA_B<1> 10C8<> 11D3<> RAM_DATA_B<2> 10C8<> 11D3<> RAM_DATA_B<3> 10C8<> 11D3<> RAM_DATA_B<4> 10C8<> 11D5<> RAM_DATA_B<5> 10C8<> 11D5<> RAM_DATA_B<6> 10C8<> 11D5<> RAM_DATA_B<7> 10C8<> 11D5<> RAM_DATA_B<8> 10C8<> 11D3<> RAM_DATA_B<15..8> 36C5> RAM_DATA_B<9> 10C8<> 11D3<> RAM_DATA_B<10> 10C8<> 11D3<> RAM_DATA_B<11>

10C8<> 11D3<>

RAM_DATA_B<39> RAM_DATA_B<40> RAM_DATA_B<41> RAM_DATA_B<42> RAM_DATA_B<43> RAM_DATA_B<44>

10C4<> 10C4<> 10C4<> 10C4<> 10C4<> 10C4<>

SND_HP_MUTE_L SND_HP_SENSE_L

11C3<> 11C3<> 11D5<> 11C5<> 11C5<> 11C5<>

37C5> 39A5> PLL_STOP_L 7C4<> 7C8<> PMU_ACK_L 14C2< 30C4<> PMU_AC_DET 30A4< 30B4<> PMU_AC_IN 30B4<> PMU_BATT0_DET_L 30B4<> PMU_BATT1_DET_L_PU 30B4<> 30D2< PMU_BATT_DET_L 30B3< 30D2< 31A4<> 39C3> PMU_BYTE 30B6< 30C7< PMU_CAPSLOCK_LED_L 30C6<> PMU_CHARGE_V 30C4<> 31B8<> PMU_CHRG_BATT_0 30C4<> 31A8<> PMU_CLK 14C2<> 30C4<> PMU_CNVSS 30B6< 30C7< PMU_U_HRESET_L 23A4< 23C4<> 30C4<> PMU_EPM 30D2< 30D4<> PMU_FROM_INT 14C2<> 30C4<> PMU_I2C_CLK 30B4<> 30C2< PMU_I2C_DATA 30B4<> 30C2< PMU_INT_L 14B5<> 14B7< 30B6<> PMU_INT_NMI 14B5<> 14B7< 30D4<> PMU_KB_RESET_IN1 30A7<>

PMU_NUMLOCK_LED_L 30C6<> PMU_OOPS 30B2< 30B4<> PMU_PME_L 14B5<> 26B8< 30B2< 30C4<> PMU_POWERUP_OK 30B4<> 30D2< PMU_POWER_UP_L 29C7<> 30C6<> 30D7< 33B8< PMU_REQ_L 14B7< 14C2> 30C4<> PMU_RESET_BUTTON_L 25B1< 30C4<> 30D2< PMU_RESET_L 30B6<> PMU_SLEEP_LED 23C4<> PMU_SLEEP_LED_L 23C2<> 30C4<> PMU_SMB_CLK 30B4<> 30C2< 31A3< PMU_SMB_DATA 30B4<> 30C2< 31A2< PMU_TO_INT 14C2<> 30C4<> POWER_UP 29C7<> POWER_VALID 30B2< 30C4<> PWR_BUTTON_L 23A7<> 25C2< 39B2> RAM_ADDR<0> 9B4< 11B5<> 11B6<> RAM_ADDR<12..0> 36A5> RAM_ADDR<1> 9B4< 11B3<> 11B8<> RAM_ADDR<2> 9B4< 11B5<> 11B6<> RAM_ADDR<3> 9B4< 11B3<> 11B8<> RAM_ADDR<4> 9B4< 11B5<> 11B6<> RAM_ADDR<5> 9B4< 11B3<> 11B8<> RAM_ADDR<6> 9B4< 11B5<> 11B6<> RAM_ADDR<7> 9B4< 11B3<> 11B8<> RAM_ADDR<8> 9B4< 11B5<> 11B6<> RAM_ADDR<9> 9A4< 11B3<> 11B8<> RAM_ADDR<10> 9A4< 11B3<> 11B8<>

6

7 14C5<> 25C4<> 14B5<> 25D6<> 39C6>

SND_HW_RESET_L 14A7< 14B5<> 25C8< 39C6> SND_HW_RESET_L_F 25C6<> 25C7< SND_LIN_SENSE_L 14B5<> 25D6<> 39C6> SND_SCLK 14B1< 25C8< 36B1> 39C6> SND_SCLK_F 25C7< 25D7<> SND_SYNC 14B1< 25D8< 39D6> SND_SYNC_F 25C7<> 25D7< SND_TO_AUDIO 14B1< 25D8< 39D6> SND_TO_AUDIO_F 25D6<> 25D7< SOFT_PWR_ON_L 22D1< 23A8< 30A8< 30C6<> 30D7< 34A3<>

VCORE_FAST<2> 34D3< 34D5< VCORE_FAST<3> 34D3< 34D5< VCORE_FAST<4> 34D3< 34D5< VCORE_FB 34B5< 38B1> 39A2> VCORE_GND 34B5<> 38B1> VCORE_GNDA 34B6<> VCORE_GNDDIV 34A4< 34B5< 38B1> VCORE_GNDDIV_TEST 34A3<> VCORE_GNDSNS 34A2<> 34A4< 38B1> VCORE_GNDSNS_TEST 34A3<> VCORE_ILIM 34C6<> 38C1> VCORE_LX 34B5<> 38C1> VCORE_MUX_EN 34D5<> 39A2>

SRCLK_TP SRMOD_TP ST7_I_SEL_PD ST7_KBD_LED_OUT ST7_OSC1

VCORE_MUX_SEL VCORE_REF VCORE_SEL_OFF_PU VCORE_SEL_ON VCORE_SHDN_L

34D5<> 34B6<> 38C1> 34B6<> 34B6<> 5C3< 34C6<>

VCORE_SLOW<1> VCORE_SLOW<2> VCORE_SLOW<3> VCORE_SLOW<4> VCORE_SNS VCORE_TIME

34D6< 34D6< 34D6< 34D6< 34A1<> 38B1> 34B4<> 38B1>

VCORE_TON VCORE_VCC VCORE_VGATE VCORE_VID0 VCORE_VID1

34B6< 38C1> 34C6< 38C1> 14B5< 14B7< 34B4> 38B1> 39A3> 39A3>

VCORE_VID2 VCORE_VID3 VCORE_VID4 VCORE_VID<0> VCORE_VID<1> VCORE_VID<2>

39A3> 39A3> 39A3> 34A2<> 34B8< 34A2<> 34B8< 34D4<> 34A2<> 34B8< 34D4<>

VCORE_VID<3> VCORE_VID<4> VGA_B VGA_G VGA_HSYNC

34A2<> 34A2<> 22C6<> 22C5<> 22C6<>

VGA_HSYNC_BUF VGA_R VGA_VSYNC VGA_VSYNC_BUF ZV_LCDDATA20_PU

22C8<> 22C5<> 22D7< 39D7> 22C5<> 22C7< 39D7> 22C8<> 19C7<>

26A5> 26A5< 23A2< 23A4< 23D5<

39A4> 39A4> 23D6< 23C4<>

ST7_OSC2 23D5<> ST7_PB6_PD 23B2< 23C4<> ST7_RESET_L 23D5<> ST7_SENSOR4_SCK_PD 23B2< 23D4<> ST7_SENSOR4_SDA_PD 23B2< 23D4<> ST7_SENSOR5_SCK_PU 23B2< 23D4<> ST7_SENSOR5_SDA_PU 23B2< 23D4<> ST7_SLEEP_LED_H 23C2<> 23C4<> ST7_XTAL_IN 23C5< STOP_AGP_L 12D2< 12D4<> SUPPLY_M_DM 25B6< 25B8< SUPPLY_M_DP 25B6< 25B8< SUTRO_ALS_GAIN_SW 23C4<> 24B2<> 39C2> SUTRO_ALS_OUT 23C4<> 24B2<> 39C2> SYSCLK_U 5C4< 8A6< 36D1> SYSCLK_U_UF 8A6<> 36D1> SYSCLK_DDRCLK_A0 9D4< 11D8<> 36D1> SYSCLK_DDRCLK_A0_L 9D4< 11D8<> 36D1> SYSCLK_DDRCLK_A0_L_UF 9B6<> 9D5< 36D1> SYSCLK_DDRCLK_A0_UF 9B6<> 9D5< 36D1> SYSCLK_DDRCLK_A1 9D4< 11A6<> 36D1> SYSCLK_DDRCLK_A1_L 9D4< 11A6<> 36D1> SYSCLK_DDRCLK_A1_L_UF 9B6<> 9D5< 36D1> SYSCLK_DDRCLK_A1_UF 9B6<> 9D5< 36D1> SYSCLK_DDRCLK_B0 9D4< 11D3<> 36D1> SYSCLK_DDRCLK_B0_L 9C4< 11D3<> 36C1> SYSCLK_DDRCLK_B0_L_UF 9B6<> 9C5< 36D1> SYSCLK_DDRCLK_B0_UF 9B6<> 9D5< 36D1>

11B5<> 11B3<> 11B3<> 11A3<> 11A3<> 11B5<>

RAM_DATA_B<55> 10C2<> 11A5<> RAM_DATA_B<56> 10C2<> 11A3<> RAM_DATA_B<63..56> 36A5> RAM_DATA_B<57> 10C2<> 11A3<> RAM_DATA_B<58> 10C2<> 11A3<> RAM_DATA_B<59> 10C2<> 11A3<> RAM_DATA_B<60> 10C2<> 11A5<> RAM_DATA_B<61> 10C2<> 11A5<> RAM_DATA_B<62> 10C2<> 11A5<> RAM_DATA_B<63> 10C2<> 11A5<> RAM_DQM_A<0> 10B8<> 11D6<> 36C5> RAM_DQM_A<1> 10C7<> 11D6<> 36C5> RAM_DQM_A<2> 10B6<> 11C6<> RAM_DQM_A<3..2> 36B5> RAM_DQM_A<3> 10C5<> 11C6<> RAM_DQM_A<4> 10B4<> 11B6<> RAM_DQM_A<5..4> 36B5> RAM_DQM_A<5> 10C3<> 11A6<> RAM_DQM_A<6> 10B2<> 11A6<> 36B5> RAM_DQM_A<7> 10C1<> 11A6<> 36A5> RAM_DQM_B<0> 10C8<> 11D5<> 36C5> RAM_DQM_B<1> 10C8<> 11D5<> 36C5> RAM_DQM_B<2> 10C6<> 11C5<> RAM_DQM_B<3..2> 36B5> RAM_DQM_B<3> 10C6<> 11C5<> RAM_DQM_B<4> 10C4<> 11B5<> RAM_DQM_B<5..4> 36B5> RAM_DQM_B<5> 10C4<> 11B5<> RAM_DQM_B<6> 10C2<> 11A5<> 36B5> RAM_DQM_B<7> 10C2<> 11A5<> 36A5> RAM_DQS_A<0> 10B8<> 11D8<> 36C5> RAM_DQS_A<1> 10C7<> 11D8<> 36C5> RAM_DQS_A<2> 10B6<> 11C8<> RAM_DQS_A<3..2> 36B5> RAM_DQS_A<3> 10C5<> 11C8<> RAM_DQS_A<4> 10B4<> 11B8<> RAM_DQS_A<5..4> 36B5> RAM_DQS_A<5> 10C3<> 11A8<> RAM_DQS_A<6> 10B2<> 11A8<> 36B5> RAM_DQS_A<7> 10C1<> 11A8<> 36A5> RAM_DQS_B<0> 10C8<> 11D3<> 36C5> RAM_DQS_B<1> 10C8<> 11D3<> 36C5> RAM_DQS_B<2> 10C6<> 11C3<> RAM_DQS_B<3..2> 36B5> RAM_DQS_B<3> 10C6<> 11C3<> RAM_DQS_B<4> 10C4<> 11B3<> RAM_DQS_B<5..4> 36B5> RAM_DQS_B<5> 10C4<> 11B3<> RAM_DQS_B<6> 10C2<> 11A3<> 36B5> RAM_DQS_B<7> 10C2<> 11A3<> 36A5> RAM_MUXSEL_H 10A3< 10A5< 10B1<> 10B3<> 36A5> RAM_MUXSEL_L 10A3< 10A5< 10B5<> 10B7<> 36A5> RAM_RAS_L 9A4< 11B5<> 11B6<> 36A5> RAM_WE_L 9A4< 11B3<> 11B8<> 36A5> RF_DISABLE_L_SPN 24D6<> 39C1> RIGHT_USB_DM 26A3< 32A7<> 37A2> 39D1> RIGHT_USB_DP 26A3< 32A7<> 37A2> 39D1> RJ45_C0_PD 27B2<> RJ45_C1_PD 27B2<> RJ45_C2_PD 27B2<> RJ45_C3_PD 27B2<> RJ45_DN<0> 27B2<> 37D2> 39B3> RJ45_DN<1> 27B2<> 37D2> 39B3> RJ45_DN<2> 27B2<> 37D2> 39A3> RJ45_DN<3> 27B2<> 37D2> 39A3> RJ45_DP<0> 27B2<> 37D2> 39B3> RJ45_DP<1> 27B2<> 37D2> 39B3> RJ45_DP<2> 27B2<> 37D2> 39A3> RJ45_DP<3> 27B2<> 37D2> 39A3> ROM_CS_L 9B3< 12A5< 24B6<> 39B1> ROM_OE_L 9B3< 12A5< 24C5<> 39B1> ROM_ONBOARD_CS_L 9B3< 24C6<> 39B1> ROM_RW_L 9B3< 12A5< 24C6<> 39B1> ROM_WP_L 9B3< RSDM3_TP 26C5> RSDM4_TP 26C5> RSDM5_TP 26C5> RSDP3_TP 26C5> RSDP4_TP 26C5> RSDP5_TP 26C5> RUN_OR_AC 29C6<> SI_A2 20B7< SI_DDC_CLK 19C5<> 20B7< SI_DDC_DATA 19C5<> 20B7< SI_EDGE 20B7< SI_MSEN 20B5<> SI_PD 20B7< SI_RST 20B7< SI_TMDS_CLKN 20B5<> 20C4< SI_TMDS_CLKP 20B5<> 20C4< SI_TMDS_DN<0> 20B5<> 20C4< SI_TMDS_DN<1> 20B5<> 20C4< SI_TMDS_DN<2> 20A5<> 20B4< SI_TMDS_DP<0> 20B5<> 20C4< SI_TMDS_DP<1> 20B5<> 20C4< SI_TMDS_DP<2> 20A5<> 20B4< SI_VREF 20A5< 20A7< SLEEP 23C4<> 25C6<> 30B6<> 30D7< 33A4< 33A6< 33B3< 33B8<> 35B3< 35D2< 39A1> SLEEP_LED SLEEP_LED_I SLEEP_LED_L SLEEP_LED_SW_L SLEEP_LED_UF SLEEP_LS5 SLEEP_LS5_EN_L SLEEP_L_LS5 SLEEP_L_LS5_EN_L SLEEP_L_LS5_INV SLEEP_L_LS5_NET SLEEP_NET SLEEP_NET_INV SMC_TP SND_AGND

23C1< 25C7<> 39B6> 23D1< 23D1< 23C2<> 23C1< 33A5<> 33A8< 33A5<> 19A7<> 27A8<> 33A5<> 34C8<> 35C8< 33A6<> 35A3< 35C2< 35C8<> 33B3<> 35C8<> 33A3<> 33A3<> 26B5< 25C7<> 38B6>

SND_AMP_MUTE SND_AMP_MUTE_F SND_AMP_MUTE_L SND_CLKOUT SND_CLKOUT_F SND_HP_MUTE SND_HP_MUTE_INV

25C8< 25D6<> 39A4> 25C7< 25D6<> 14C5<> 25D5<> 14B1< 25D8< 36B1> 39D6> 25C7<> 25D7< 25C5<> 25C5<> 25C6<> 39A4>

5

34B8< 34B8< 22D7< 22D7< 22C7<

4

3

2

1

D

34D4<> 34D4<> 39D7> 39D7> 39D7>

SYSCLK_DDRCLK_B1 9D4< 11A5<> 36C1> SYSCLK_DDRCLK_B1_L 9D4< 11A5<> 36C1> SYSCLK_DDRCLK_B1_L_UF 9B6<> 9D5< 36D1> SYSCLK_DDRCLK_B1_UF 9B6<> 9D5< 36D1> SYSCLK_LA_TP 8A6<> SYSTEM_CLK_EN TEB_TP TEST_TP THERM1_A_DM THERM1_A_DP THERM1_DM THERM1_DP THERM1_M_DM THERM1_M_DP THERM2_A_DM THERM2_A_DP THERM2_DM THERM2_DP THERM2_M_DM THERM2_M_DP THERM_INV THERM_L_OC TMDS_CLKN TMDS_CLKP TMDS_CLK_CMF TMDS_CONN_CLKN TMDS_CONN_CLKP TMDS_CONN_DN<0> TMDS_CONN_DN<1> TMDS_CONN_DN<2> TMDS_CONN_DP<0> TMDS_CONN_DP<1> TMDS_CONN_DP<2> TMDS_D0_CMF TMDS_D1_CMF TMDS_D2_CMF TMDS_DN<0>

14A5< 14A7< 30C4<> 26A5< 39A4> 26A5< 39A4> 25A6< 25A8< 37A2> 25A6< 25A8< 37A2> 25A5< 25A5< 25B5< 25B5<> 37A2> 25A5< 25A5< 25B5< 25B5<> 37A2> 37A2> 37A2> 25A6< 25A8< 37A2> 25A6< 25A8< 37A2> 25A5< 25B5< 25B5<> 37A2> 25A5< 25B5< 25B5<> 37A2> 37A2> 37A2> 25A5<> 25A4<> 30B4<> 20B3< 20C1< 20C3< 22B7<> 37B2> 20B3< 20C2< 20C3< 22C7<> 37B2> 20C1< 22B6<> 22C7<> 37B2> 39A8> 22C6<> 22C7<> 37B2> 39D7> 22C7<> 22D6<> 22B7<> 22D5<> 22B6<> 22D5<> 22B7<> 22D6<> 22B7<> 22D5<> 22B6<> 22D5<> 20B1< 20B1< 20A1< 20B1< 20B3< 20C3< 22C8<> 37B2> 39B8> TMDS_DN<1> 20A3< 20B1< 20C3< 22B8<> 37B2> 39A8> TMDS_DN<2> 20A1< 20A3< 20B3< 22B7<> 37B2> 39A8> TMDS_DP<0> 20B2< 20B3< 20C3< 22B8<> 37B2> 39A8> TMDS_DP<1> 20A3< 20B2< 20C3< 22B8<> 37B2> 39A8> TMDS_DP<2> 20A2< 20A3< 20B3< 22B7<> 37B2> 39A8> TPAD_F_RXD 23A7<> 39C4> TPAD_F_TXD 23A7<> 39C4> TPAD_RXD 23A8< 30C2< 30C4<> TPAD_TXD 23A8< 30B2< 30C4<> TPS2211_SHDN_L_PU 17C4< TV_C 22A6<> 39D6> TV_COMP 22A6<> 39D6> TV_GND1 22B6<> 38B6> 39A7> TV_GND2 22A6<> 38B6> 39A7> TV_Y 22A6<> 39D6> UIDE_ADDR<0> 13D7<> 24C4< UIDE_ADDR<2..0> 37C5> UIDE_ADDR<1> 13D7<> 24C4< UIDE_ADDR<2> 13D7<> 24B4< UIDE_CS0_L 13C7<> 24C4< 37C5> UIDE_CS1_L 13C7<> 24B4< 37C5> UIDE_DATA<0> 13D7<> 24D4< UIDE_DATA<6..0> 37C5> UIDE_DATA<1> UIDE_DATA<2> UIDE_DATA<3> UIDE_DATA<4> UIDE_DATA<5> UIDE_DATA<6> UIDE_DATA<7> UIDE_DATA<8> UIDE_DATA<15..8> UIDE_DATA<9> UIDE_DATA<10> UIDE_DATA<11> UIDE_DATA<12> UIDE_DATA<13> UIDE_DATA<14> UIDE_DATA<15> UIDE_DIOR_L UIDE_DIOW_L UIDE_DMACK_L UIDE_DMARQ UIDE_INTRQ UIDE_IOCHRDY UIDE_REF UIDE_RST_L USB2_PCI_GNT_L USB2_PCI_INT_L USB2_PCI_REQ_L USB_D1M USB_D1P USB_D2M USB_D2P USB_DAM USB_DAP USB_DBM USB_DBP USB_DCM USB_D USB_DDM USB_DDP USB_DEM USB_DEP USB_DFM USB_DFP USB_OC_AB_L USB_OC_CD_L USB_OC_EF_L USB_PWREN_AB_L USB_PWREN_CD_L USB_PWREN_EF_L

13D7<> 24D4< 13D7<> 24D4< 13D7<> 24D4< 13D7<> 24C4< 13D7<> 24C4< 13D7<> 24C4< 13D7<> 24C4< 37C5> 13D7<> 24C4< 37C5> 13D7<> 24C4< 13D7<> 24C4< 13D7<> 24D4< 13D7<> 24B4< 13D7<> 24B4< 13D7<> 24C4< 13D7<> 24B4< 13C7<> 24A4< 37C5> 13C7<> 24A4< 37C5> 13C7<> 24A4< 37C5> 13C7<> 37C5> 13C7< 37C5> 13C7< 24A4< 37C5> 13C7<> 38D3> 13C7<> 24A4< 37C5> 12C7<> 26B7< 14B5<> 14C7< 26A8< 12A7< 12D7<> 26B7> 14C1< 26A5> 26B4< 14C1< 26A4< 26A5> 14D1< 26A4< 26A5> 14D1< 26A4< 26A5> 14B2<> 14D2< 26A5> 14B2<> 14D2< 26A5> 14B2<> 14D2< 14B2<> 14D2< 14B2<> 14C2< 26A5> 14B2<> 14C2< 26A5> 14B2<> 14C2< 14B2<> 14C2< 14B2< 14B2<> 37B2> 14B2<> 14C2< 37B2> 14B2< 14B2<> 37B2> 14B2< 14B2<> 37B2> 14B2< 14C7< 14B2< 14C7< 14B2< 14D7< 14B2<> 14C7< 14B2<> 14C7< 14B2<> 14D7<

VCORE_BOOST VCORE_BST VCORE_CC VCORE_CNTL_RC VCORE_DH VCORE_DL

34C4<> 34C5<> 34B6<> 19A3<> 34B5<> 34B5<>

VCORE_FAST<1>

34D3< 34D5<

C

B

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

38C1> 38C1> 38B1>

SIZE

38C1> 38C1>

APPLE COMPUTER INC.

DRAWING NUMBER

D

SHT NONE

7

6

5

4

3

2

REV.

051-6598

SCALE

8

A

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

01 OF

42 42

1

44

8

D

C

B

A

6

7

2

3

4

5

*** Part Cross-Reference for the entire design ***

C166 C167

CAP CAP

19 19

BS1 C1 C2 C3 C4

PCB_STANDOFF 4 CAP 22 CAP 34 CAP 34 CAP 34

C168 C169 C170 C171 C172

CAP CAP CAP CAP CAP

5 5 5 16 16

C334 C335 C336 C337 C338 C339 C340

CAP CAP CAP CAP CAP CAP CAP

16 16 16 16 19 21 5

C502 C503 C504 C505 C506 C507 C508


27 27 27 27 27 34 33

C670 C671 C672 C673 C674 C675 C676


23 21 21 23 34 23 22

C838 C839 C840 C841 C842 C843 C844


26 26 26 26 26 26 26

L26 L27 L28 L29 L30 L31 L32

IND IND IND IND IND_3P IND IND

22 22 22 22 19 22 22

C5 C6 C7 C8 C9 C10

CAP CAP CAP CAP CAP CAP

34 34 34 5 16 16

C173 C174 C175 C176 C177 C178


16 16 16 16 16 16

C341 C342 C343 C344 C345 C346


5 5 5 5 5 5

C509 C510 C511 C512 C513 C514


32 32 27 34 25 19

C677 C678 C679 C680 C681 C682


35 25 34 34 25 34

C845 C846 C847 C848 C849 C850


26 25 21 21 21 21

L33 L34 L35 L36 L37 L38

IND IND IND IND_3P IND_3P IND

C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26

CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP

18 5 34 20 14 16 16 16 16 16 16 16 16 16 5 16



16 16 16 14 16 16 16 19 19 5 5 5 5 5 5 5



5 16 16 16 16 16 14 16 16 16 16 21 21 21 21 21



19 33 27 34 35 27 34 11 11 11 11 11 11 29 34 11


CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP_P CAP CAP CAP CAP

35 22 22 14 34 25 34 25 14 14 34 33 34 22 33 14



21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21

L39 L40 L41 L42 L43 L44 L45 L46 L47 L48 L49 L50 L51 L52 L53 L54

C27 C28 C29 C30 C31 C32


16 16 16 16 16 16

C195 C196 C197 C198 C199 C200


5 16 16 14 16 14

C363 C364 C365 C366 C367 C368


21 21 16 16 16 16

C531 C532 C533 C534 C535 C536


35 33 33 33 32 32

C699 C700 C701 C702 C703 C704


34 33 21 22 22 21

C867 C868 C869 C870 C871 C872


21 21 21 21 21 21

C33 C34 C35 C36 C37

CAP CAP CAP CAP CAP

16 16 16 16 18

C38 C39 C40 C41 C42 C43


5 5 5 5 16 16

C201 C202 C203 C204 C205 C206 C207 C208 C209 C210 C211

CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP

5 5 5 16 16 16 16 16 16 16 16

C369 C370 C371 C372 C373 C374 C375 C376 C377 C378 C379


16 16 16 21 21 21 16 16 16 16 21

C537 C538 C539 C540 C541 C542 C543 C544 C545 C546 C547


32 28 28 28 28 11 21 35 33 28 31

C705 C706 C707 C708 C709 C710 C711 C712 C713 C714 C715


35 22 22 19 35 22 25 22 22 22 21

C873 C874 C875 C876 C877 C878 C879 C880 C881 C882 C883


C44 C45 C46 C47 C48

CAP CAP CAP CAP CAP

16 16 5 5 5

C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 C65

CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP

16 16 16 16 16 16 16 16 16 16 16 16 16 18 18 18 18

C212 C213 C214 C215 C216 C217 C218 C219 C220 C221 C222 C223 C224 C225 C226 C227 C228 C229 C230 C231 C232 C233

CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP

16 16 16 16 16 16 20 19 19 19 19 5 5 5 16 16 16 16 16 16 19 20



21 21 21 21 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16



11 11 11 11 22 32 32 27 29 31 30 35 33 28 31 31 31 11 33 33 32 32


CAP CAP CAP CAP_P CAP_P CAP_P CAP CAP CAP CAP CAP CAP CAP_P CAP_P CAP_P CAP_P CAP_P CAP_P CAP_P CAP CAP CAP

21 22 22 19 19 19 21 35 22 21 35 10 34 34 34 34 34 34 34 10 10 10


CAP_P CAP_P CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP

C66 C67 C68 C69 C70 C71 C72 C73 C74 C75 C76


18 18 18 18 18 18 5 5 5 16 16

16 16 16 16 16 16 21 21 16 21 21

C570 C571 C572 C573 C574 C575 C576 C577 C578 C579 C580


28 28 31 11 30 35 33 28 31 31 35

C738 C739 C740 C741 C742 C743 C744 C745 C746 C747 C748

CAP CAP CAP CAP CAP CAP CAP CAP_P CAP CAP CAP

10 22 35 10 10 10 22 35 22 10 10

C906 C907 C908 C909 D1 D2 D3 D4 D5 D6 D7

CAP 31 CAP 35 CAP 35 CAP 5 DIODE 27 DIODE_SCHOT 34 DIODE_SCHOT 32 DIODE 32 DIODE_SCHOT 19 DIODE_SCHOT 33 DIODE_SCHOT 32

18 18 20 20 20 20 12 14 14 24 20 20 20 5 5 5 35 16 16 16 14 16 16 16 16 20 5 5 5 5 5 16 16 5 5 5 5 5 5 34 16 16 16 16 16 16 16 16 16 16 16 16 20 20 20

34 35 16 16 16 16 16 16 16 16 16 9 16 12 16 16 16 16 19 19 19 20 19 5 5 16 16 16 16 16 16 16 16 16 16 19 19 19


CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP

CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP

C402 C403 C404 C405 C406 C407 C408 C409 C410 C411 C412

C77 C78 C79 C80 C81 C82 C83 C84 C85 C86 C87 C88 C89 C90 C91 C92 C93 C94 C95 C96 C97 C98 C99 C100 C101 C102 C103 C104 C105 C106 C107 C108 C109 C110 C111 C112 C113 C114 C115 C116 C117 C118 C119 C120 C121 C122 C123 C124 C125 C126 C127 C128 C129 C130 C131

C234 C235 C236 C237 C238 C239 C240 C241 C242 C243 C244 C245 C246 C247 C248 C249 C250 C251 C252 C253 C254 C255 C256 C257 C258 C259 C260 C261 C262 C263 C264 C265 C266 C267 C268 C269 C270 C271 C272 C273 C274 C275 C276 C277 C278 C279 C280 C281 C282 C283 C284 C285 C286 C287 C288 C289 C290 C291 C292 C293 C294 C295 C296 C297 C298 C299

CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP

5 5 34 5 35 16 16 16 16 16 19 5 20 34 16 16 16 16 16 16 16 16 16 16 16 16 16 19


CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP_P CAP CAP CAP_P CAP_P CAP_P CAP CAP CAP CAP CAP CAP CAP CAP CAP_P CAP CAP_P CAP_P CAP_P CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP

21 21 21 22 16 16 14 21 21 16 16 14 21 21 34 21 21 34 34 34 14 21 21 21 21 21 34 22 34 27 34 34 34 21 21 19 22 21 19 22 27 27 34 33 27 31 34 9 32 32 32 27 27 27 17


CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP

35 35 33 32 32 28 28 29 11 33 28 31 31 11 11 11 11 33 32 31 11 11 35 32 28 29 29 31 33 33 33 33 32 28 31 31 31 31 31 33 31 31 33 31 32 32 28 28 28 31 31 31 31 28 28


CAP CAP_P CAP_P CAP CAP CAP CAP CAP_P CAP CAP_P CAP CAP CAP CAP CAP CAP CAP_P CAP CAP CAP CAP_P CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP_P CAP CAP_P CAP CAP CAP CAP CAP CAP_P CAP CAP CAP CAP CAP_P CAP_P CAP CAP CAP CAP CAP_P CAP CAP CAP CAP

22 32 35 10 10 27 27 33 31 32 33 33 11 19 33 34 32 19 25 34 32 33 31 31 17 29 31 17 28 28 33 35 29 35 17 29 33 29 32 35 17 17 17 29 32 32 17 17 17 17 32 33 32 31 29

C132 C133 C134 C135 C136 C137 C138 C139 C140 C141 C142 C143 C144 C145 C146 C147 C148 C149 C150 C151 C152 C153 C154 C155 C156 C157 C158

CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP

20 20 25 25 5 5 5 5 14 16 16 16 16 16 16 16 14 5 5 5 5 5 5 5 5 16 16



19 19 19 19 21 19 19 19 8 16 16 19 16 16 16 16 16 16 16 16 16 16 16 16 16 16 19



31 25 9 27 27 19 22 27 27 27 25 9 16 11 11 19 22 32 27 27 27 11 11 27 27 27 19



23 23 23 33 28 28 28 30 32 28 28 21 23 26 28 25 31 28 23 23 23 26 31 33 23 26 33


CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP_P CAP_P CAP_P CAP_P CAP_P CAP_P CAP_P CAP_P CAP CAP CAP CAP CAP

28 29 33 29 28 35 28 33 30 17 23 23 23 31 28 32 32 32 32 33 31 33 33 30 23 26 26

D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D33 D34 DP1 DP2 DP3 DP4 DP5 DP6 DP7 F1 F2 F3 F4 F5 FL1 FL2 FL3 G1 G2 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J22 J23 J24 J25 J26 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15

ZENER 29 DIODE 31 DIODE 31 DIODE_SCHOT 32 DIODE_DUAL_6P 29 DIODE_SCHOT 33 DIODE_SCHOT_3P2 28 DIODE_DUAL_6P 29 DIODE 33 DIODE_SCHOT 32 DIODE 32 DIODE_SCHOT 32 DIODE_SCHOT 28 DIODE_SCHOT 22 DIODE_SCHOT 33 DIODE_SCHOT 35 DIODE_SCHOT 19 DIODE 34 DIODE_DUAL_6P 29 DIODE_SCHOT 32 DIODE_DUAL_6P 29 DIODE_SCHOT 29 DIODE_SCHOT 31 DIODE_SCHOT 35 DIODE_SCHOT 33 DPAK3P 19 DPAK3P 34 DPAK3P 35 DPAK3P 31 DPAK3P 29 DPAK3P 19 DPAK3P 21 FUSE 22 FUSE 29 FUSE 31 FUSE 31 FUSE 29 FILTER_LC 22 FILTER_LC 22 FILTER_LC 22 OSC 28 OSC 18 CON_F1ST_S2MT_SM 14 CON_3RTSM_125 25 CON_F14RT_S2MT_SM 24 CON_3RTSM_125 25 CON_12 34 CON_F30RT_S2MT_SM 22 CON_4RT_WRIB 22 CON_F16ST_D_SMA 25 CON_M80ST_D4MT_SM 17 CON_M50SM_5MM 24 CON_F14RT_S2MT_SM 32 CON_F30ST_D_SM 25 CON_M50SM_5MM 24 CON_F30RT_T6MT_TH1 22 CON_F5RT_MINIDIN_TH 22 CON_10STSM_5087 25 CON_RJ45_SHORT_4MT_TH 27 CON_M8RT_S_SM 31 CON_F200RT_DDRDIMM_SM1 11 CON_F80ST_D4MT_SM 24 CON_F200RT_DDRDIMM_SM2 11 CON_F6RT_S4MT_TH1 29 CON_F40RT_S2MT_SM 23 CON_M8RT_S_SM 31 CON_F9RT_1394B_S6MT_SMA 29 IND 14 IND 18 IND 18 IND 18 IND 27 IND 22 IND 28 IND 31 IND 31 IND 31 IND 23 IND 31 IND 20 IND 20 IND 20

C159 C160 C161 C162 C163 C164


16 12 16 16 16 16

C327 C328 C329 C330 C331 C332


21 19 19 19 19 19

C495 C496 C497 C498 C499 C500


32 27 27 34 35 22

C663 C664 C665 C666 C667 C668


23 30 26 30 26 25

C831 C832 C833 C834 C835 C836


30 30 26 26 30 26

L16 L18 L21 L22 L23 L24

IND IND FILTER_4P IND IND IND

C165

CAP

20

C333

CAP

19

C501

CAP

27

C669

CAP

22

C837

CAP

26

L25

IND

1

R27 R28

RES RES

7 14

R195 R196

RES RES

18 8

RES RES RES RES RES RES RES RES RES RES RES

14 24 24 24 7 13 24 24 18 18 23

R197 R198 R199 R200 R201

RES RES RES RES RES

8 9 9 18 18

22 27 35 34 32 33

R29 R30 R31 R32 R33 R34 R35 R36 R37 R38 R39

R202 R203 R204 R205 R206 R207

RES RES RES RES RES RES

20 19 20 20 5 8

IND IND IND IND FILTER_4P FILTER_4P IND IND IND IND IND IND IND IND IND IND

29 29 33 31 29 29 35 23 23 23 23 29 28 23 31 26

R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55

RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES

23 20 25 18 18 18 18 7 7 14 14 13 13 18 18 18



8 12 20 20 20 22 20 8 12 12 20 20 20 19 20 19

L55 L56 L57 L58 L59 L60

IND IND IND IND IND IND

21 21 21 21 21 21

R56 R57 R58 R59 R60 R61


26 5 5 5 5 5

R224 R225 R226 R227 R228 R229


20 8 8 8 19 19

21 21 21 21 21 21 21 21 21 19 31

L61 L62 L63 L64 L65 L66 L67 L68 L69 L70 L71

IND IND IND IND IND IND IND IND IND FILTER_4P FILTER_4P

21 21 21 21 21 21 21 21 21 29 29

R62 R63 R64 R65 R66 R67 R68 R69 R70 R71 R72


23 24 24 5 20 14 24 24 18 24 5

34 34 35 35 35 21 35 35 35 35 35 25 25 25 25 25 25 25 19 25 25 25

L72 L73 L74 L75 L76 L77 L78 L79 L80 L81 L82 PD1 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10

FILTER_4P 22 FILTER_4P 22 FILTER_4P 22 IND 35 IND 25 IND 25 IND 25 IND 25 IND 25 IND 25 IND 25 PHOTODIODE_2P 23 TRA_2N7002DW 7 TRA_2N7002DW 7 TRA_2N7002 7 TRA_2N3904 7 TRA_2N3904 19 TRA_2N3904 19 TRA_FDG6324L 22 TRA_2N7002 22 TRA_2N7002DW 33 TRA_2N7002DW 31

R73 R74 R75 R76 R77 R78 R79 R80 R81 R82 R83 R84 R85 R86 R87 R88 R89 R90 R91 R92 R93 R94

RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES

5 24 24 24 12 26 5 14 24 12 26 26 5 5 5 20 14 14 14 13 24 24

R230 R231 R232 R233 R234 R235 R236 R237 R238 R239 R240 R241 R242 R243 R244 R245 R246 R247 R248 R249 R250 R251 R252 R253 R254 R255 R256 R257 R258 R259 R260 R261 R262

RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES

12 20 20 20 19 20 19 20 9 10 19 5 10 10 14 19 19 19 19 19 9 21 10 19 19 21 19 19 19 19 19 19 19

Q11 Q12 Q13 Q14 Q15 Q16 Q17 Q19 Q20 Q21 Q22 Q23 Q24 Q25 Q26 Q27 Q28 Q29 Q30 Q31 Q32 Q33 Q35 Q36 Q37 Q38 Q39 Q40 Q41 Q42 Q43 Q44 Q45 Q46 Q47 Q48 Q49 Q50 Q51 Q52 Q53 Q54 Q55 Q56

TRA_SI3443DV 22 TRA_2N3904 34 TRA_SI4435DY 31 TRA_FDG6324L 32 TRA_2N7002DW 27 TRA_SI4435DY 31 TRA_2N3904 34 TRA_2N7002 35 TRA_2N7002DW 31 TRA_2N7002DW 31 TRA_2N7002 30 TRA_2N7002DW 33 TRA_SI4435DY 31 TRA_2N7002DW 29 33 TRA_2N7002DW 25 TRA_2N7002DW 31 TRA_SI3443DV 33 TRA_2N7002DW 31 TRA_2N7002DW 31 TRA_2N7002DW 25 TRA_SI3443DV 33 TRA_2N3906 23 TRA_2N7002DW 22 23 TRA_SI3446DV 25 TRA_SI3446DV 25 TRA_2N7002DW 22 TRA_2N3904 25 TRA_TP0610 22 TRA_2N7002DW 22 TRA_2N3904 22 TRA_SI3443DV 33 TRA_2N3904 22 TRA_TP0610 22 TRA_SI3446DV 35 TRA_2N3904 25 TRA_SI7892DP 19 TRA_SI7860DP 34 TRA_SI7860DP 34 TRA_SI7860DP 19 TRA_SI4888DY 33 TRA_IRF7832 34 TRA_IRF7832 34 TRA_IRF7832 34 TRA_IRF7811W 35

R95 R96 R97 R98 R99 R100 R101 R102 R103 R104 R105 R106 R107 R108 R109 R110 R111 R112 R113 R114 R115 R116 R117 R118 R119 R120 R121 R122 R123 R124 R125 R126 R127 R128 R129 R130 R131 R132 R133 R134 R135 R136 R137 R138

RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES

24 26 5 5 20 14 24 14 12 18 18 5 5 5 5 20 14 12 14 14 14 24 13 18 18 5 8 8 8 13 14 18 18 5 5 5 8 8 8 8 8 8 8 18

R263 R264 R265 R266 R267 R268 R269 R270 R271 R272 R273


19 14 19 19 34 21 19 19 19 19 19

Q57 Q58 Q59 Q60 Q61 Q62 Q63 Q64 Q65 Q66 Q67 Q68 Q69 Q71 Q72 Q73 Q74 Q75 Q76 Q77 Q78 Q79

TRA_IRF7805 35 TRA_2N7002DW 29 TRA_IRF7805 32 TRA_IRF7811W 32 TRA_SI4888DY 33 TRA_2N3904 25 TRA_IRF7805 31 TRA_IRF7811W 31 TRA_2N7002DW 31 TRA_2N3904 25 TRA_NDS9407 29 TRA_IRF7811W 35 TRA_IRF7805 35 TRA_SI4888DY 33 TRA_SI4888DY 33 TRA_2N3906 23 TRA_2N3906 23 TRA_2N7002DW 23 TRA_SUD45P03 31 TRA_SI3446DV 19 TRA_2N7002DW 25 TRA_2N7002DW 33



5 8 8 8 8 8 13 12 12 5 7 8 8 8 8 13 14 14 12 18 18 5

R274 R275 R276 R277 R278 R279 R280 R281 R282 R283 R284 R285 R286 R287 R288 R289 R290 R291 R292 R293 R294 R295 R296 R297 R298 R299 R300 R301 R302 R303 R304 R305 R306 R307 R308 R309 R310 R311 R312 R313 R314 R315 R316 R317 R318 R319 R320 R321 R322 R323 R324 R325 R326 R327 R328

RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES

19 5 5 14 14 21 5 14 5 5 21 14 26 15 34 34 34 14 34 25 19 25 33 34 33 21 33 34 34 34 34 34 19 19 33 33 33 19 34 34 34 34 19 22 34 27 22 34 34 34 34 34 34 34 34

Q80 Q81 Q82 Q83 Q84 Q85 Q86 Q87 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19

TRA_2N7002DW 19 TRA_2N7002DW 33 TRA_2N7002DW 35 TRA_2N7002DW 35 TRA_SI6467BDQ 35 TRA_SI6467BDQ 35 TRA_2N7002DW 34 TRA_2N7002DW 25 RES 22 RES 7 RES 7 RES 7 RES 7 RES 23 RES 14 RES 24 RES 7 RES 7 RES 7 RES 7 RES 7 RES 7 RES 7 RES 7 RES 7 RES 7 RES 7

R161 R162 R163 R164 R165 R166 R167 R168 R169 R170 R171 R172 R173 R174 R175 R176 R177 R178 R179 R180 R181 R182 R183 R184 R185 R186 R187

RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES

8 8 8 8 8 8 8 14 12 12 12 18 18 8 8 8 8 8 8 12 18 8 8 8 12 12 12



34 34 34 19 27 27 27 34 34 9 19 19 19 22 27 27 27 27 27 17 34 33 19 19 27 27 27

21 14 22 14 22 19

R20 R21 R22 R23 R24 R25


7 7 7 7 7 7

R188 R189 R190 R191 R192 R193


18 18 35 9 12 12

R356 R357 R358 R359 R360 R361


34 9 31 32 32 27

22

R26

RES

7

R194

RES

12

R362

RES

27

D

C

B

A

43

8

7

6

5

4

3

2

1

8

D

C

B

A

6

7

4

5

R363 R364 R365 R366 R367 R368 R369

RES RES RES RES RES RES RES

31 31 31 34 33 33 33

R531 R532 R533 R534 R535 R536 R537


26 23 23 23 30 30 25

R703 R704 R705 R706 R707 R708 R709


22 22 22 22 14 14 35

RP58 RP59 RP60 RP61 SH1 SP1 SP2

RPAK2P 20 RPAK2P 20 RPAK2P 20 RPAK2P 20 SHLD_3P_EMI 4 SPKR_CLIP_P84 4 SPKR_CLIP_P84 4

ZT73 ZT74 ZT75 ZT76 ZT77 ZT78 ZT79

HOLE_VIA HOLE_VIA HOLE_VIA HOLE_VIA HOLE_VIA HOLE_VIA HOLE_VIA

4 4 4 4 4 4 4

R370 R371 R372 R373 R374 R375


27 27 27 17 31 31

R538 R539 R540 R541 R542 R543


33 33 26 32 31 31

R710 R711 R712 R713 R714 R715


25 19 35 25 22 35

SP3 SP4 SP5 SP6 T1 U1

SPKR_CLIP_P84 4 SPKR_CLIP_P84 4 SPKR_CLIP_P84 4 SPKR_CLIP_P84 4 XFR_ENET_1000BT 27 SN74AUC1G04 7

ZT80 ZT81 ZT82 ZT83

HOLE_VIA HOLE_VIA HOLE_VIA MTGHOLE

4 4 4 4



34 33 33 32 27 27 27 31 34 34 9 9 19 19 19 22



30 26 28 28 31 31 23 26 23 25 26 28 28 28 31 31



25 25 22 25 14 21 21 25 22 25 25 35 21 21 24 33

U2 U3 U4 U5 U6

SN74AUC1G08 23 ADT7460 25 SN74AUC1G08 23 SIL1162 20 FAN2558 5

U7 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18

VREG_LT1962 14 CBTV4020 10 CBTV4020 10 PI3B3257 34 CBTV4020 10 CBTV4020 10 LTC3405 27 COMPARATOR_LMC7211 31 LTC1778 19 FEPR_1MX8 9 LTC1625 32

R392 R393 R394 R395 R396 R397


32 27 31 31 31 34

R560 R561 R562 R563 R564 R565


31 31 30 28 28 31

R732 R733 R734 R735 R736 R737


34 27 31 27 29 29

U19 U20 U21 U22 U23 U24

PWR_CNTRL_TPS2211 17 MAX1717 34 COMPARATOR_LMC7211 32 MAX1715 35 AMP_MAX4172 31 7432 22 30

R398 R399 R400 R401 R402 R403 R404 R405 R406 R407 R408 R409 R410 R411 R412 R413 R414 R415 R416 R417 R418 R419 R420 R421 R422 R423 R424 R425 R426 R427 R428 R429 R430

RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES

34 15 22 32 32 27 27 25 27 34 34 9 19 24 32 27 31 34 19 35 35 35 35 35 35 35 35 35 32 27 27 34 19

R566 R567 R568 R569 R570 R571 R572 R573 R574 R575 R576


31 31 23 30 31 31 30 30 28 28 28

R738 R739 R740 R741 R742 R743 R744 R745 R746 R747 R748


31 31 28 29 31 29 31 24 31 31 31

U25 U26 U27 U28 U29 U30 U31 U32 U33 U34 U35

VREG_LP2951 32 PCI1510GGU 17 COMPARATOR_LMC7211 30 LTC3707 33 TSB81BA3A 28 VREG_LP2951 32 MAX1772 31 EEPROM_16KX8_M24128B 23 M16C62 30 VREG_LM2594 28 MAX1916 23



28 31 31 31 23 23 30 30 30 26 23 31 33 26 26 30 30 30 30 30 30 23



31 17 29 29 17 31 31 17 17 28 28 28 28 17 31 17 30 17 17 30 30 23

U36 U37 U38 U39 U40

LTC1761 28 VREG_LT1962 28 COMPARATOR_LMC7211 31 UPD720101_FBGA 26 OPAMP_MAX4236EUTT 23

U42 U43 U44 U45 U46 U47 U49 U50 U51 U52 U54 U55 U56 U57 U58 XW1 XW2

CLK_GEN_CY28512 14 APOLLO_MPC7447A_360 5 6 RAGE_MBLTY_M11_CSP64_667 18 19 21 INTREPID 8 9 12 13 14 15 COMPARATOR_LMC7211 22 CLK_GEN_CY25811 18 TRANSCEIVER_88E1111 27 OPAMP_LMC7111 31 MAX6804 30 FEPR_256KX8_ST72264_BGA 23 VREG_MM1571J 21 VREG_MM1571J 21 741G32 22 741G32 22 LTC3412 35 SHORT 35 SHORT 19

R431 R432 R433 R434 R435 R436 R437 R438 R439 R440 R441


33 32 32 34 27 28 28 27 9 11 24

R599 R600 R601 R602 R603 R604 R605 R606 R607 R608 R609


31 26 24 24 24 14 23 23 35 14 14

R771 R772 R773 R774 R775 R776 R777 R778 R779 R781 R782


23 23 23 31 28 23 23 30 29 28 30

XW3 XW4 XW5 XW6 XW7 XW8 XW9 XW11 XW12 XW13 XW15

SHORT SHORT SHORT SHORT SHORT SHORT SHORT JUMPER SHORT SHORT SHORT

34 32 34 35 34 33 25 35 22 22 34



24 32 28 28 28 28 34 11 35 19 24 29 31 35 33 33 24 28 31 35 33 33 28 27 31 33 32 28 28 28 29 31 31 30 30 33 28 35 35 33 33 32 28 28 28 31 31 31 31 30 30 35 28 28 28



35 35 24 24 14 23 35 23 23 23 25 13 14 25 13 14 13 35 25 13 13 14 14 27 14 14 14 8 8 8 8 8 8 8 8 8 22 22 8 8 8 8 22 14 8 8 8 8 22 22 22 8 8 8 8

31 19 19 19 19 19 21 21 21 21 5 14 27 23 26 30

Y7 ZT1 ZT2 ZT3 ZT4 ZT5 ZT6 ZT7 ZT8 ZT9 ZT10 ZT11 ZT12 ZT13 ZT14 ZT15 ZT16 ZT17 ZT18 ZT19 ZT20 ZT21 ZT22 ZT23 ZT24 ZT25 ZT26 ZT27 ZT28 ZT29 ZT30 ZT31 ZT32 ZT33 ZT34 ZT35 ZT36 ZT37 ZT38

CRYSTAL_4PIN 30 HOLE_VIA 4 MTGHOLE 4 HOLE_VIA 4 MTGHOLE 4 MTGHOLE 4 MTGHOLE 4 HOLE_VIA 4 HOLE_VIA 4 HOLE_VIA 4 MTGHOLE 4 MTGHOLE 4 HOLE_VIA 4 HOLE_VIA 4 HOLE_VIA 4 HOLE_VIA 4 MTGHOLE 4 HOLE_VIA 4 HOLE_VIA 4 HOLE_VIA 4 HOLE_VIA 4 HOLE_VIA 4 HOLE_VIA 4 HOLE_VIA 4 HOLE_VIA 4 HOLE_VIA 4 HOLE_VIA 4 HOLE_VIA 4 HOLE_VIA 4 HOLE_VIA 4 HOLE_VIA 4 HOLE_VIA 4 HOLE_VIA 4 HOLE_VIA 4 HOLE_VIA 4 HOLE_VIA 4 HOLE_VIA 4 HOLE_VIA 4 HOLE_VIA 4

31 31 31 9 30 30 30 30 30 33 33 32 28 28 31 31 30 33 33 28 30 30 33 33 32 28 33

R668 R669 R670 R671 R672

RES RES RES RES RES

8 8 22 22 35

R673 R674 R675 R676 R677 R678


8 8 8 8 8 8



25 22 22 14 8 8 8 22 22 25 22 22 25 5 22 25

26 26 30 30 30 30 26 26 26 26 26 26 26 26 35 35 35 35 35 35 35 19 34 34 34 34 34 35 25 25 25 25 14 24 24 24 24 14 14 14 24 24 24 13 24 13 13 13 12 12 12 12 8 12 8 8 14 9 9 20 20 14 9 9 20 9 9 9 9 28 28 17 30 30 23 23 25 26 14 14 14 24 24

SHORT SHORT SHORT SHORT SHORT SHORT SHORT SHORT SHORT SHORT SHORT CRYSTAL CRYSTAL CRYSTAL CRYSTAL CRYSTAL


RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RPAK4P RPAK4P RPAK4P RPAK4P RPAK4P RPAK4P RPAK4P RPAK4P RPAK4P RPAK4P RPAK4P RPAK4P RPAK4P RPAK4P RPAK4P RPAK4P RPAK4P RPAK4P RPAK4P RPAK4P RPAK4P RPAK4P RPAK4P RPAK4P RPAK4P RPAK4P RPAK2P RPAK2P RPAK4P RPAK4P RPAK4P RPAK2P RPAK4P RPAK4P RPAK4P RPAK4P RPAK4P RPAK4P RPAK10P2C RPAK4P RPAK4P RPAK10P2C RPAK10P2C RPAK4P RPAK4P RPAK4P RPAK4P RPAK4P RPAK4P RPAK4P

XW19 XW20 XW21 XW22 XW23 XW24 XW27 XW28 XW29 XW30 XW31 Y1 Y3 Y4 Y5 Y6


R783 R784 R785 R786 R787 R788 R789 R790 R791 R792 R793 R794 R795 R796 R797 R798 R799 R800 R801 R802 R803 R804 R805 R806 R807 R808 R809 R810 R811 R812 R813 R814 RP1 RP2 RP3 RP4 RP5 RP6 RP7 RP8 RP9 RP10 RP11 RP12 RP13 RP14 RP15 RP16 RP17 RP18 RP19 RP20 RP21 RP22 RP23 RP24 RP25 RP26 RP27 RP28 RP29 RP30 RP31 RP32 RP33 RP34 RP35 RP36 RP37 RP38 RP39 RP40 RP41 RP42 RP43 RP44 RP45 RP46 RP47 RP48 RP49 RP50

ZT39 ZT40 ZT41 ZT42 ZT43 ZT44 ZT45 ZT46 ZT47 ZT48 ZT49 ZT50 ZT51 ZT52 ZT53 ZT54 ZT55 ZT56 ZT57 ZT58 ZT59 ZT60 ZT61 ZT62 ZT63 ZT64 ZT65

HOLE_VIA HOLE_VIA HOLE_VIA HOLE_VIA HOLE_VIA HOLE_VIA HOLE_VIA HOLE_VIA HOLE_VIA HOLE_VIA HOLE_VIA HOLE_VIA HOLE_VIA HOLE_VIA HOLE_VIA HOLE_VIA HOLE_VIA HOLE_VIA HOLE_VIA HOLE_VIA HOLE_VIA HOLE_VIA HOLE_VIA HOLE_VIA HOLE_VIA HOLE_VIA HOLE_VIA

4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4

R524 R525 R526 R527 R528 R529


28 28 31 25 33 33

R696 R697 R698 R699 R700 R701


22 33 14 14 22 14

RP51 RP52 RP53 RP54 RP55 RP56

RPAK4P RPAK4P RPAK4P RPAK4P RPAK4P RPAK4P

14 23 26 23 26 26 14

ZT66 ZT67 ZT68 ZT69 ZT70 ZT71

HOLE_VIA HOLE_VIA HOLE_VIA HOLE_VIA HOLE_VIA HOLE_VIA

4 4 4 4 4 4

R530

RES

26

R702

RES

5

RP57

RPAK2P

20

ZT72

HOLE_VIA

4

3

2

1

D

C

B

A

44

8

7

6

5

4

3

2

1

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