Lpc-link-ii Schematic Rev C 5w1y4j
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Overview 4q3b3c
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More details 26j3b
- Words: 1,307
- Pages: 6
Page 2
Design Overview
Power supplies
LPC-Link II
Page 3
External powering (+5V)
USB 2.0 interface, LPC4320 USB, reset, crystal, jtag/swd 3.3V
External powering (+3.3V)
Power supplies USB powering External jtag/swd interface
Page 4 Boot mode, LPC4320 IOs
3.3V External jtag/swd/trace connector USB mini-B
Analog channel LPC4320 power supplies
LPC4320 IOs Digital channels
Page 5
Serial Expansion Interface LPC4320 JTAG/SWD connector LPC4320 crystal, reset
External nor flash, external spi flash
External SPI flash LED
Page 6 Analog channel, digital channels, jtag/swd/trace interface
Schematic page 2-3
Schematic page 4
UL = UnLoaded = normally not mounted component.
Default jumper settings are indicated in the schematic. However, always check jumper positions on actual boards since there is no guarantee that all jumpers are in default place.
10/2/2012 3:59:32 PM f=0.68 C:\Eagle\Link-II_v2\LPC-Link-II_Rev_C.sch (Sheet: 1/6)
Schematic page 5-6
NXP Semiconductors
Power Supply Access connector
D3 PMEG3005EJ
J1 TP_3V3
USB_VBUS D2 PMEG3005EJ
JP3 not installed 1
EXT_POW U8 4
5V0
Power supply
3
VROUT
C34
C35 10n
GND
GND
LPC4320_NRESET VIO_3V3 VIO_3V3Z 5V0
2
CE
TAB
NC
GND
R53
5 TAB
C36
2
10n
J1 not installed
1 2 3 4 5 6 7
GND
VIO_3V3
0R C37 22u
GND
TX6227C331PR-G
10u
EXT_POW
JP3
VIN
1
TP_GND
GND GND
GND L1 VIO_3V3 BLM15HG601SN1D U1_POWER
C2 C8 D4 D5 G8 J3 J6
LPC4320 power supplies
VDDIO VDDIO VSSA VDDREG VDDREG VDDREG
VSS VSS VSS VSS VSS VSS
VDDA VBAT
F10 K5
VIO_3V3
E4 E5 F4
VDDREG
L4 VIO_3V3 BLM15HG601SN1D
B2 VDDA C5
LPC4320-TFBGA100_2 GND
C19
C16
C25
C21
C24
C28
C26
C23
100n
100n
100n
22n
10u
100n
22n
100n
GND
GND
GND
GND
GND
GND
GND
GND
C29 10u GND
U9
Target Power supply
4
5V0
1 3
VIN
VROUT
CE
TAB
NC
GND
5
VIO_3V3Z
TAB
NXP Semiconductors
2
TX6227C331PR-G C38
C39
C41
C40
10u
10n
22u
10n
GND
GND
GND
GND
GND
10/2/2012 3:59:32 PM f=0.68 C:\Eagle\Link-II_v2\LPC-Link-II_Rev_C.sch (Sheet: 2/6)
USB 2.0 OTG Interface
45 ohm impedance routing, 90 ohm differential No tracks within 10 times trace width No via's and no sharp angles L3 USB_VBUS BLM15AG121SN1D USB-DM USB-DP
+5V 1 2 3 4 5
LPC4320 USB
U1_USB R39 E3 E2 E1 F1 F3
100R R41
USB_ID
USB0_VBUS USB0_DM USB0_DP USB0_ID USB0_RREF
USB0_VDDA3V3 USB0_VDDA3V3_DRIVER USB0_VSSA_REF USB0_VSSA_TERM
D2 VIO_3V3 D1 VIO_3V3 F2 D3
C9
C11
10u
100n
C13 39n
1M
R2
10n/500V
GND
GND
12K1
R42
C1 GND
GND
LPC4320-TFBGA100_2 1M
3u3
1M
C20
100n
R25
C8
R40
LINE2
VCC
LINE1
0R GND
GND
GND
C27
C22
10u
GND
D1 PRTR5V0U2X
GND
GND
GND
3n3 GND
GND GND
LPC4320 reset, crystal, JTAG/SWD
LED
4K7
USB1_DM
K3 K6
LPC4320_CLK0 LPC4320_CLK2 LPC4320_WAKEUP0 R4 EXP_ADC0_DAC 2k2 R3 EXP_ADC1 2k2 R6 EXP_ADC2 2k2 R5 EXP_ADC3 2k2
A4 A2 A1 B3 A3
ADC0 ADC1 ADC2 ADC3 C17
C18
C14
C15
100p
100p
100p
100p
DP1 DM1 CLK0 CLK2
XTAL1 XTAL2
WAKEUP0 RESET# ADC0 ADC1 ADC2 ADC3
RTCX1 RTCX2 RTC_ALARM
B4 G3 C4 H2 H3 A6
LPC4320_TRST LPC4320_TDI LPC4320_TMS LPC4320_TCK LPC4320_TDO LPC4320_DBGEN
FTSH-105-01-L-DV VIO_3V3
B6 LPC4320_NRESET
LPC4320-TFBGA100_2
C10 18p
TP_RST TP_RTCX1
GND
TP_RTCX2
4K7
R26
4K7
R27
TP_RTC_ALARM
LPC4320_DBGEN
1 3 5 7 9
LPC4320_TRST
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C12 18p
2 4 6 8 10
J2
Y1 ABLS-12.000MHZ-B2-T
VIO_3V3
VIO_3V3 GND
R7 0R
B1 XTAL1 C1 XTAL2
A5 B5 C3
R45
R28
E9 E10
USB1_DP
TRST# TDI TMS TCK TDO DBGEN
SCL SDA
LPC4320_TMS LPC4320_TCK LPC4320_TDO LPC4320_TDI LPC4320_NRESET
2K2 LED1 LTST-C191KRKT
TP_CLK
E6
I2C_SDA
4K7
TP_WAKEUP TP_CLK2
I2C_SCL D6
TP_DP1
BOOT0_LED
U1_MISC
R29
TP_DM1
4K7
R30
VIO_3V3
GND
GND
GND
NXP Semiconductors
Boot mode - DFU USB0 (0b0101) - SPIFI (0b0001) 2K2 R43
UL R44
UL R54
2K2 R55
2K2
R9 R32
R31
UL
R8
2K2
VIO_3V3
UL
2
JP1
1
BOOT0_LED BOOT1 BOOT2 BOOT3
GND
GND GND GND GND
LPC4320 IOs U1_PORT
H1 K2 K1 J1 J2 J4 K4 G4 H5 J5 H6 J7 K7 H8 J8 K8 H9 H10 J10 K9 K10
SGPIO0_SGPIO4_TRACEDATA0 SGPIO1_SGPIO5_TRACEDATA1 SGPIO2_SGPIO6_TRACEDATA2 ISP_CTRL SGPIO_13
G10 G7 F5 D8 D9
PF_4
P1_0 P1_1 P1_2 P1_3 P1_4 P1_5 P1_6 P1_7 P1_8 P1_9 P1_10 P1_11 P1_12 P1_13 P1_14 P1_15 P1_16 P1_17 P1_18 P1_19 P1_20
P6_0 P6_1 P6_2 P6_4 P6_5 P6_9 P6_11
P2_0 P2_1 P2_2 P2_3 P2_4
H4
SSP1_SCK
H7 G5 J9 F6 F9 F8 C9
CLK GPIO3_0 GPIO3_1 GPIO3_3 GPIO3_4 GPIO3_5 GPIO3_7
A8 F7 G6 A7 B8 B7 C7 D7 E7
CLK_1 GPIO5_8 GPIO5_9 SPIFI_SCK SPIFI_SIO3 SPIFI_SIO2 SPIFI_MISO SPIFI_MOSI SPIFI_CS
D10 G9 C10 C6 B10 E8 A9 B9 A10
GPIO5_5_JTAG_RESET GPIO5_6_JTAG_RESET_TXEN ISP_N BOOT2 BOOT3 UART2_TXD UART2_RXD GPIO1_12 GPIO1_13
TP_P6_0 VIO_3V3
P3_0 P3_1 P3_2 P3_3 P3_4 P3_5 P3_6 P3_7 P3_8 P2_5 P2_6 P2_7 P2_8 P2_9 P2_10 P2_11 P2_12 P2_13
C4
External SPI Flash
10u GND
TP_P3_0
C3 100n GND
U2
VIO_3V3
SPIFI_CS
1
SPIFI_MISO
2
SPIFI_SIO2
3 4
UL
TP_P1_19
SGPIO3_SGPIO7_TRACEDATA3 BOOT0_LED BOOT1 SSP1_MISO SSP1_MOSI SGPIO15_TMS_SWDIO_TXEN SGPIO14_TMS_SWDIO GPIO1_0 GPIO1_1 GPIO1_2 GPIO1_3 GPIO1_4 SGPIO8_TRACECLK_RTCK SGPIO_9 SGPIO10_TDO_SWO SGPIO2_SGPIO6_TRACEDATA2 SGPIO3_SGPIO7_TRACEDATA3 SGPIO11_TCK_SWCLK SGPIO12_JTAG_TDI CGU_CLKOUT SSP1_SEL
P0_0 P0_1
R1
SGPIO0_SGPIO4_TRACEDATA0 G2 SGPIO1_SGPIO5_TRACEDATA1 G1
TP_ISP
CE#
VDD
SO/SIO1
SIO3
SIO2
SCK
VSS
SI/SIO0
8 7
SPIFI_SIO3
6
SPIFI_SCK
5
SPIFI_MOSI
W25Q80BVSSIG GND
LPC4320-TFBGA100_2
NXP Semiconductors
10/2/2012 3:59:33 PM f=0.68 C:\Eagle\Link-II_v2\LPC-Link-II_Rev_C.sch (Sheet: 4/6)
U3 1
VIO_3V3 SGPIO11_TCK_SWCLK
2
DIR_U3
5
VCC_B
A1 B1
8
7
VIO_BUF_B 100R
JTAG_TCK_SWCLK
R17
DIR
R57 GND
JTAG/SWD/TRACE Interface
4
100K 3
SGPIO12_JTAG_TDI
A2 B2
6
5
GND 100R
JTAG_TDI
VCC
VIO_3V3 U5P 3
R18
GND
VIO_3V3
VCC_A
GND FTSH-105-01-L-DV
74LVC2T45DC U4
JTAG_VREF VIO_BUF_B 100K
TRACECLK_RTCK
5
SGPIO0_SGPIO4_TRACEDATA0
A3
B3
19
FTSH-110-01-L-DV
C30 100n GND
TRACEDATA0
1 3 5 7 9 11 13 15 17 19
C42 100n GND
0R
R22
20
GND
R23
B2
JTAG_TMS_SWDIO JTAG_TCK_SWCLK JTAG_TDO_SWO JTAG_TDI JTAG_RESET
J7
DIR
A2
2 4 6 8 10
74LVC1G07DCK
R21 4
SGPIO8_TRACECLK_RTCK
ISP_CTL_OD
R46
JTAG_TDO_SWO
100K
B1
VIO_BUF_B
21
4
100K
A1
23
2
ISP_CTRL
100K
2
VCC_B
U5
VIO_BUF_B
100K
DIR_U4
OE
24
100K
3
R56
SGPIO10_TDO_SWO
VCC_B
R19
22
VCC_A
R20
1
VIO_3V3
1 3 5 7 9
JTAG_TMS_SWDIO JTAG_TCK_SWCLK JTAG_TDO_SWO JTAG_TDI JTAG_RESET TRACECLK_RTCK TRACEDATA0 TRACEDATA1 TRACEDATA2 TRACEDATA3
B4
18
TRACEDATA1
GND
R38
GND
VIO_3V3ZZ
2
A4
J8 GND
2
6
SGPIO1_SGPIO5_TRACEDATA1
C31 100n
UL
C32 JP2 open - Target supplied JTAG_VREF JP2 closed - Target powered by JTAG_VREF 10u
JP2
1
VIO_BUF_B
2 4 6 8 10 12 14 16 18 20
7
SGPIO2_SGPIO6_TRACEDATA2
A5
B5
17
TRACEDATA2
VIO_3V3Z
C7
1
SJ4
3
100n D4 PMEG1020EA
J6 Not installed GND
8
SGPIO3_SGPIO7_TRACEDATA3
A6
B6
16
100K
R24
VIO_BUF_B
EXT_POW
VIO_3V3
1
SGPIO14_TMS_SWDIO
3
A7
B7
15
SGPIO_9_BUF
B8
14
GND
VIO_3V3
1
GPIO5_5_JTAG_RESET
3
GPIO5_6_JTAG_RESET_TXEN 5 GND
13
B
GND
GND
4
100R
VCC_A
VCC_B
B
JTAG_TMS_SWDIO
GND
2
R48
6
4
100R R49
DIR GND
10/2/2012 3:59:33 PM f=0.68 C:\Eagle\Link-II_v2\LPC-Link-II_Rev_C.sch (Sheet: 5/6)
1X09
GND 100K
A
74LVC1T45GW
ISP_CTL_OD VIO_BUF_B
R51
DIR
74LVC8T245PW GND
R50
6
74LVC1T45GW U6
SGPIO_13_BUF
GND
A
R47
11 12
A8
2k2
10
VCC_B
GND
GND
SGPIO_13
VCC_A
R52
9
2k2
SGPIO15_TMS_SWDIO_TXEN 5 SGPIO_9
100K
U7
TRACEDATA3
1 J6 2 3 4 5 6 7 8 9
2
GND
VIO_BUF_B JTAG_RESET
NXP Semiconductors
Digital channels
Analog + Digital channels
L5 FTSH-112-01-L-DV
C33 C6
C5
3u3
100n
100n 1
FTSH-110-01-L-DV 1 3 5 7 9 11 13 15 17 19
2 4 6 8 10 12 14 16 18 20
2 4 6 8 10 12 14 16 18 20 22 24
3 5 7 9 11 13 15 17 19 21 23
VDDA EXP_ADC0_DAC EXP_ADC1 EXP_ADC2 EXP_ADC3 DIR_U4 DIR_U3 SGPIO_9_BUF SGPIO_13_BUF
VIO_3V3Z BLM15AG121SN1D
GPIO1_0 GPIO1_1 GPIO1_2 GPIO1_3 GPIO1_4 GPIO1_12 GPIO1_13 GPIO3_0 GPIO3_1 GPIO3_3 GPIO3_4
J9 J4
GND
GND
Serial Expansion Interface L2 VIO_3V3Z BLM15AG121SN1D
C2 100R
SSP1_SCK SSP1_MISO UART2_RXD I2C_SCL GPIO5_8 GPIO3_5
100R
1 3 5 7 9 11 13
R11 100R 100R
R12
R13 100R 100R
FTSH-107-01-L-DV
100R
100n
R10
R14
2 4 6 8 10 12 14
J3
R15
100R
R33
R34 100R 100R
R35
R36 100R 100R
R37
SSP1_MOSI SSP1_SEL UART2_TXD I2C_SDA GPIO5_9 GPIO3_7
R16 GND
NXP Semiconductors
10/2/2012 3:59:33 PM f=0.68 C:\Eagle\Link-II_v2\LPC-Link-II_Rev_C.sch (Sheet: 6/6)
Design Overview
Power supplies
LPC-Link II
Page 3
External powering (+5V)
USB 2.0 interface, LPC4320 USB, reset, crystal, jtag/swd 3.3V
External powering (+3.3V)
Power supplies USB powering External jtag/swd interface
Page 4 Boot mode, LPC4320 IOs
3.3V External jtag/swd/trace connector USB mini-B
Analog channel LPC4320 power supplies
LPC4320 IOs Digital channels
Page 5
Serial Expansion Interface LPC4320 JTAG/SWD connector LPC4320 crystal, reset
External nor flash, external spi flash
External SPI flash LED
Page 6 Analog channel, digital channels, jtag/swd/trace interface
Schematic page 2-3
Schematic page 4
UL = UnLoaded = normally not mounted component.
Default jumper settings are indicated in the schematic. However, always check jumper positions on actual boards since there is no guarantee that all jumpers are in default place.
10/2/2012 3:59:32 PM f=0.68 C:\Eagle\Link-II_v2\LPC-Link-II_Rev_C.sch (Sheet: 1/6)
Schematic page 5-6
NXP Semiconductors
Power Supply Access connector
D3 PMEG3005EJ
J1 TP_3V3
USB_VBUS D2 PMEG3005EJ
JP3 not installed 1
EXT_POW U8 4
5V0
Power supply
3
VROUT
C34
C35 10n
GND
GND
LPC4320_NRESET VIO_3V3 VIO_3V3Z 5V0
2
CE
TAB
NC
GND
R53
5 TAB
C36
2
10n
J1 not installed
1 2 3 4 5 6 7
GND
VIO_3V3
0R C37 22u
GND
TX6227C331PR-G
10u
EXT_POW
JP3
VIN
1
TP_GND
GND GND
GND L1 VIO_3V3 BLM15HG601SN1D U1_POWER
C2 C8 D4 D5 G8 J3 J6
LPC4320 power supplies
VDDIO VDDIO VSSA VDDREG VDDREG VDDREG
VSS VSS VSS VSS VSS VSS
VDDA VBAT
F10 K5
VIO_3V3
E4 E5 F4
VDDREG
L4 VIO_3V3 BLM15HG601SN1D
B2 VDDA C5
LPC4320-TFBGA100_2 GND
C19
C16
C25
C21
C24
C28
C26
C23
100n
100n
100n
22n
10u
100n
22n
100n
GND
GND
GND
GND
GND
GND
GND
GND
C29 10u GND
U9
Target Power supply
4
5V0
1 3
VIN
VROUT
CE
TAB
NC
GND
5
VIO_3V3Z
TAB
NXP Semiconductors
2
TX6227C331PR-G C38
C39
C41
C40
10u
10n
22u
10n
GND
GND
GND
GND
GND
10/2/2012 3:59:32 PM f=0.68 C:\Eagle\Link-II_v2\LPC-Link-II_Rev_C.sch (Sheet: 2/6)
USB 2.0 OTG Interface
45 ohm impedance routing, 90 ohm differential No tracks within 10 times trace width No via's and no sharp angles L3 USB_VBUS BLM15AG121SN1D USB-DM USB-DP
+5V 1 2 3 4 5
LPC4320 USB
U1_USB R39 E3 E2 E1 F1 F3
100R R41
USB_ID
USB0_VBUS USB0_DM USB0_DP USB0_ID USB0_RREF
USB0_VDDA3V3 USB0_VDDA3V3_DRIVER USB0_VSSA_REF USB0_VSSA_TERM
D2 VIO_3V3 D1 VIO_3V3 F2 D3
C9
C11
10u
100n
C13 39n
1M
R2
10n/500V
GND
GND
12K1
R42
C1 GND
GND
LPC4320-TFBGA100_2 1M
3u3
1M
C20
100n
R25
C8
R40
LINE2
VCC
LINE1
0R GND
GND
GND
C27
C22
10u
GND
D1 PRTR5V0U2X
GND
GND
GND
3n3 GND
GND GND
LPC4320 reset, crystal, JTAG/SWD
LED
4K7
USB1_DM
K3 K6
LPC4320_CLK0 LPC4320_CLK2 LPC4320_WAKEUP0 R4 EXP_ADC0_DAC 2k2 R3 EXP_ADC1 2k2 R6 EXP_ADC2 2k2 R5 EXP_ADC3 2k2
A4 A2 A1 B3 A3
ADC0 ADC1 ADC2 ADC3 C17
C18
C14
C15
100p
100p
100p
100p
DP1 DM1 CLK0 CLK2
XTAL1 XTAL2
WAKEUP0 RESET# ADC0 ADC1 ADC2 ADC3
RTCX1 RTCX2 RTC_ALARM
B4 G3 C4 H2 H3 A6
LPC4320_TRST LPC4320_TDI LPC4320_TMS LPC4320_TCK LPC4320_TDO LPC4320_DBGEN
FTSH-105-01-L-DV VIO_3V3
B6 LPC4320_NRESET
LPC4320-TFBGA100_2
C10 18p
TP_RST TP_RTCX1
GND
TP_RTCX2
4K7
R26
4K7
R27
TP_RTC_ALARM
LPC4320_DBGEN
1 3 5 7 9
LPC4320_TRST
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C12 18p
2 4 6 8 10
J2
Y1 ABLS-12.000MHZ-B2-T
VIO_3V3
VIO_3V3 GND
R7 0R
B1 XTAL1 C1 XTAL2
A5 B5 C3
R45
R28
E9 E10
USB1_DP
TRST# TDI TMS TCK TDO DBGEN
SCL SDA
LPC4320_TMS LPC4320_TCK LPC4320_TDO LPC4320_TDI LPC4320_NRESET
2K2 LED1 LTST-C191KRKT
TP_CLK
E6
I2C_SDA
4K7
TP_WAKEUP TP_CLK2
I2C_SCL D6
TP_DP1
BOOT0_LED
U1_MISC
R29
TP_DM1
4K7
R30
VIO_3V3
GND
GND
GND
NXP Semiconductors
Boot mode - DFU USB0 (0b0101) - SPIFI (0b0001) 2K2 R43
UL R44
UL R54
2K2 R55
2K2
R9 R32
R31
UL
R8
2K2
VIO_3V3
UL
2
JP1
1
BOOT0_LED BOOT1 BOOT2 BOOT3
GND
GND GND GND GND
LPC4320 IOs U1_PORT
H1 K2 K1 J1 J2 J4 K4 G4 H5 J5 H6 J7 K7 H8 J8 K8 H9 H10 J10 K9 K10
SGPIO0_SGPIO4_TRACEDATA0 SGPIO1_SGPIO5_TRACEDATA1 SGPIO2_SGPIO6_TRACEDATA2 ISP_CTRL SGPIO_13
G10 G7 F5 D8 D9
PF_4
P1_0 P1_1 P1_2 P1_3 P1_4 P1_5 P1_6 P1_7 P1_8 P1_9 P1_10 P1_11 P1_12 P1_13 P1_14 P1_15 P1_16 P1_17 P1_18 P1_19 P1_20
P6_0 P6_1 P6_2 P6_4 P6_5 P6_9 P6_11
P2_0 P2_1 P2_2 P2_3 P2_4
H4
SSP1_SCK
H7 G5 J9 F6 F9 F8 C9
CLK GPIO3_0 GPIO3_1 GPIO3_3 GPIO3_4 GPIO3_5 GPIO3_7
A8 F7 G6 A7 B8 B7 C7 D7 E7
CLK_1 GPIO5_8 GPIO5_9 SPIFI_SCK SPIFI_SIO3 SPIFI_SIO2 SPIFI_MISO SPIFI_MOSI SPIFI_CS
D10 G9 C10 C6 B10 E8 A9 B9 A10
GPIO5_5_JTAG_RESET GPIO5_6_JTAG_RESET_TXEN ISP_N BOOT2 BOOT3 UART2_TXD UART2_RXD GPIO1_12 GPIO1_13
TP_P6_0 VIO_3V3
P3_0 P3_1 P3_2 P3_3 P3_4 P3_5 P3_6 P3_7 P3_8 P2_5 P2_6 P2_7 P2_8 P2_9 P2_10 P2_11 P2_12 P2_13
C4
External SPI Flash
10u GND
TP_P3_0
C3 100n GND
U2
VIO_3V3
SPIFI_CS
1
SPIFI_MISO
2
SPIFI_SIO2
3 4
UL
TP_P1_19
SGPIO3_SGPIO7_TRACEDATA3 BOOT0_LED BOOT1 SSP1_MISO SSP1_MOSI SGPIO15_TMS_SWDIO_TXEN SGPIO14_TMS_SWDIO GPIO1_0 GPIO1_1 GPIO1_2 GPIO1_3 GPIO1_4 SGPIO8_TRACECLK_RTCK SGPIO_9 SGPIO10_TDO_SWO SGPIO2_SGPIO6_TRACEDATA2 SGPIO3_SGPIO7_TRACEDATA3 SGPIO11_TCK_SWCLK SGPIO12_JTAG_TDI CGU_CLKOUT SSP1_SEL
P0_0 P0_1
R1
SGPIO0_SGPIO4_TRACEDATA0 G2 SGPIO1_SGPIO5_TRACEDATA1 G1
TP_ISP
CE#
VDD
SO/SIO1
SIO3
SIO2
SCK
VSS
SI/SIO0
8 7
SPIFI_SIO3
6
SPIFI_SCK
5
SPIFI_MOSI
W25Q80BVSSIG GND
LPC4320-TFBGA100_2
NXP Semiconductors
10/2/2012 3:59:33 PM f=0.68 C:\Eagle\Link-II_v2\LPC-Link-II_Rev_C.sch (Sheet: 4/6)
U3 1
VIO_3V3 SGPIO11_TCK_SWCLK
2
DIR_U3
5
VCC_B
A1 B1
8
7
VIO_BUF_B 100R
JTAG_TCK_SWCLK
R17
DIR
R57 GND
JTAG/SWD/TRACE Interface
4
100K 3
SGPIO12_JTAG_TDI
A2 B2
6
5
GND 100R
JTAG_TDI
VCC
VIO_3V3 U5P 3
R18
GND
VIO_3V3
VCC_A
GND FTSH-105-01-L-DV
74LVC2T45DC U4
JTAG_VREF VIO_BUF_B 100K
TRACECLK_RTCK
5
SGPIO0_SGPIO4_TRACEDATA0
A3
B3
19
FTSH-110-01-L-DV
C30 100n GND
TRACEDATA0
1 3 5 7 9 11 13 15 17 19
C42 100n GND
0R
R22
20
GND
R23
B2
JTAG_TMS_SWDIO JTAG_TCK_SWCLK JTAG_TDO_SWO JTAG_TDI JTAG_RESET
J7
DIR
A2
2 4 6 8 10
74LVC1G07DCK
R21 4
SGPIO8_TRACECLK_RTCK
ISP_CTL_OD
R46
JTAG_TDO_SWO
100K
B1
VIO_BUF_B
21
4
100K
A1
23
2
ISP_CTRL
100K
2
VCC_B
U5
VIO_BUF_B
100K
DIR_U4
OE
24
100K
3
R56
SGPIO10_TDO_SWO
VCC_B
R19
22
VCC_A
R20
1
VIO_3V3
1 3 5 7 9
JTAG_TMS_SWDIO JTAG_TCK_SWCLK JTAG_TDO_SWO JTAG_TDI JTAG_RESET TRACECLK_RTCK TRACEDATA0 TRACEDATA1 TRACEDATA2 TRACEDATA3
B4
18
TRACEDATA1
GND
R38
GND
VIO_3V3ZZ
2
A4
J8 GND
2
6
SGPIO1_SGPIO5_TRACEDATA1
C31 100n
UL
C32 JP2 open - Target supplied JTAG_VREF JP2 closed - Target powered by JTAG_VREF 10u
JP2
1
VIO_BUF_B
2 4 6 8 10 12 14 16 18 20
7
SGPIO2_SGPIO6_TRACEDATA2
A5
B5
17
TRACEDATA2
VIO_3V3Z
C7
1
SJ4
3
100n D4 PMEG1020EA
J6 Not installed GND
8
SGPIO3_SGPIO7_TRACEDATA3
A6
B6
16
100K
R24
VIO_BUF_B
EXT_POW
VIO_3V3
1
SGPIO14_TMS_SWDIO
3
A7
B7
15
SGPIO_9_BUF
B8
14
GND
VIO_3V3
1
GPIO5_5_JTAG_RESET
3
GPIO5_6_JTAG_RESET_TXEN 5 GND
13
B
GND
GND
4
100R
VCC_A
VCC_B
B
JTAG_TMS_SWDIO
GND
2
R48
6
4
100R R49
DIR GND
10/2/2012 3:59:33 PM f=0.68 C:\Eagle\Link-II_v2\LPC-Link-II_Rev_C.sch (Sheet: 5/6)
1X09
GND 100K
A
74LVC1T45GW
ISP_CTL_OD VIO_BUF_B
R51
DIR
74LVC8T245PW GND
R50
6
74LVC1T45GW U6
SGPIO_13_BUF
GND
A
R47
11 12
A8
2k2
10
VCC_B
GND
GND
SGPIO_13
VCC_A
R52
9
2k2
SGPIO15_TMS_SWDIO_TXEN 5 SGPIO_9
100K
U7
TRACEDATA3
1 J6 2 3 4 5 6 7 8 9
2
GND
VIO_BUF_B JTAG_RESET
NXP Semiconductors
Digital channels
Analog + Digital channels
L5 FTSH-112-01-L-DV
C33 C6
C5
3u3
100n
100n 1
FTSH-110-01-L-DV 1 3 5 7 9 11 13 15 17 19
2 4 6 8 10 12 14 16 18 20
2 4 6 8 10 12 14 16 18 20 22 24
3 5 7 9 11 13 15 17 19 21 23
VDDA EXP_ADC0_DAC EXP_ADC1 EXP_ADC2 EXP_ADC3 DIR_U4 DIR_U3 SGPIO_9_BUF SGPIO_13_BUF
VIO_3V3Z BLM15AG121SN1D
GPIO1_0 GPIO1_1 GPIO1_2 GPIO1_3 GPIO1_4 GPIO1_12 GPIO1_13 GPIO3_0 GPIO3_1 GPIO3_3 GPIO3_4
J9 J4
GND
GND
Serial Expansion Interface L2 VIO_3V3Z BLM15AG121SN1D
C2 100R
SSP1_SCK SSP1_MISO UART2_RXD I2C_SCL GPIO5_8 GPIO3_5
100R
1 3 5 7 9 11 13
R11 100R 100R
R12
R13 100R 100R
FTSH-107-01-L-DV
100R
100n
R10
R14
2 4 6 8 10 12 14
J3
R15
100R
R33
R34 100R 100R
R35
R36 100R 100R
R37
SSP1_MOSI SSP1_SEL UART2_TXD I2C_SDA GPIO5_9 GPIO3_7
R16 GND
NXP Semiconductors
10/2/2012 3:59:33 PM f=0.68 C:\Eagle\Link-II_v2\LPC-Link-II_Rev_C.sch (Sheet: 6/6)
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