Dram 2u2z70

Semiconductor Memory Types Semiconductor Memories

Read/Write (R/W) Memory or Random Access Memory (RAM)

Dynamic RAM (DRAM)

1

Static RAM (SRAM)

Read-Only Memory (ROM)

1. Mask (Fuse) ROM 2. Programmable ROM (PROM) Erasable PROM (EPROM) Electrically Erasable PROM (EEPROM) 3. Flash Memory 4. Ferroelectric RAM (FRAM)

• Design Issues – Area Efficiency of Memory Array: of stored data bits per unit area – Memory Access Time: the time required to store and/or retrieve a particular data bit. – Static and Dynamic Power Consumption • RAM: the stored data is volatile

– DRAM • A capacitor to store data, and a transistor to access the capacitor • Need refresh operation • Low cost, and high density  it is used for main memory

– SRAM • Consists of a latch • Don’t need the refresh operation • High speed and low power consumption it is mainly used for cache memory and memory in hand-held devices 2

Random-Access Memory Array Organization Bit Lines(2M) Col 1 Col 2

Col 2M

(2N2M total) Row 2N Data Line Control Circuits Column Decoder

3

Row 2

B1 B2 Column Decoder Bits

BM

Word Lines(2N)

AN

Word Decoder

Memory Cell

A1 A2 Row Decoder

Row Decoder Bits

Row 1

Dynamic Read-Write Memory (DRAM) Circuits SRAM :- 4- 6 transistors per bit 4- 5 lines connecting as charge on capacitor

DRAM :- Data bit is stored as charge on capacitor Reduced area Require periodic refresh Dynamic random-access memory (DRAM) is a type of randomaccess memory that stores each bit of data in a separate capacitor within an integrated circuit.

DRAM read operations

– Precharge bit line to VDD/2. – Take the word line HIGH. – Detect whether current flows into or out of the cell. – Note: cell contents are destroyed by the read! – Must write the bit value back after reading.

DRAM write operations

– Take the word line HIGH. – Set the bit line LOW or HIGH to store 0 or 1. – Take the word line LOW. – Note: The stored charge for a 1 will eventually leak off.

DRAM charge leakage

• Typical devices require each cell to be refreshed once every 4 to 64 mS. • During “suspended” operation, notebook computers use power mainly for DRAM refresh.

How DRAM refresh works ? • •

• • •

To maintain data integrity, it is necessary to refresh each DRAM memory cell. The read process in DRAM is destructive and removes the charge on the memory cells in an entire row, so there is a row of specialized latches on the chip called Sense amplifiers, one for each column of memory cells, to temporarily hold the data. So the normal read electronics on the chip has the ability to refresh an entire row of memory in parallel, significantly speeding up the refresh process. A normal read or write cycle refreshes a row of memory, but normal memory accesses cannot be relied on to hit all the rows within the necessary time, necessitating a separate refresh process. Rather than use the normal read cycle in the refresh process, to save time an abbreviated cycle called a refresh cycle is used.

2 Types Refresh Methods :1. Burst refresh - is done by performing a series of refresh cycles until all rows have been accessed. For the example given above, this is done every 8ms. During the refresh, other commands are not allowed. 2. Distributed refresh - refresh cycles are performed at regular intervals, interspersed with memory accesses.Using the distributed method and the above example, a refresh is done every 12.6μs (8ms divided by 512).

Operation of Three-Transistor DRAM Cell VDD Precharge devices

MP1

MP2

PC RS

M3

M1

M2

C2

C3

C1

WS Data_in

Data_out

DATA

– The binary information is stored as the charge in C1 – Storage transistor M2 is on or off depending on the charge in C1 – transistors M1 and M3: access switches 10 – Two separate bit lines for “data read” and “data write”

Operation of Three-Transistor DRAM Cell (Cont.) PC

VDD MP1

①

Precharge devices

MP2

PC

③

read 1 4

PC

⑤

write 0 6

PC

⑦

WS

DATA

M3 M2

C2

PC

PC

RS M1

write 1 2

C3

Din

C1

Stored data

WS Data_in DATA

Data_out

RS Dout

– The operation is based on a two-phase non-overlapping clock scheme • The precharge events are driven by 1, and the “read” and “write” operations are driven by 2. • Every “read” and “write” operation is preceded by a precharge cycle, which is initiated with PC going high. 11

read 0 8

Operation of One-Transistor DRAM Cell WL

M1

Column C2 capacitance

C1

BL

1-bit DRAM Cell C2>>C1

– Write “1” OP: BL = 1, WL = 1 (M1 ON)C1 charges to “1” – Write “0” OP: BL = 0, WL = 1 (M1 ON)C1 discharges to “0” – Read OP: destroys stored charge on C1  destructive refresh is needed after every data read operation 12

Write "1"

Read "1"

WL X

- VT

V

GND

DD

BL

VDD/2

VDD

VDD/2

DV =

small perturbation VDD /2

sensing

CS VDD/2 -----------------------C S + CBL

Voltage swing is small; typically around 100~ 200 mV.

Different Version of DDRAMS Types

Typical voltage

Bus Clock(MHz)

Transfer Rate ( MegaTransfer/second)

Prefetch

DIMM(dual inline memory module) Pins

DDR

2.5 V

100-200

200-400

2n

184

DDR2

1.8 V

200-533

400-1066

4n

240

DDR3

1.5 V

400-1066

800-2133

8n

240

DDR4

1.2 V

1066-2133

2133-4266

8n

288

*Prefetch - Dynamic Memories store data inside an array of tiny capacitors. DDR Memories transfer 2 bits of data per clock cycle from the memory array to the memory internal I/O buffer. This is called 2-bit Prefetch

Volatile Memory Comparison The primary difference between different memory types is the bit cell. • SRAM Cell • DRAM Cell addr

bit line • • • • • •

word line

word line

data

bit line

Larger cell  lower density, higher cost/bit No dissipation Read non-destructive No refresh required Simple read  faster access Standard IC process  natural for integration with logic

bit line • • • • •

Smaller cell  higher density, lower cost/bit Needs periodic refresh, and refresh after read Complex read  longer access time Special IC process  difficult to integrate with logic circuits Density impacts addressing 15

References:1. 2.

CMOS Digital Integrated Circuit by Sung-Mo kang and Yusuf Leblebici. en.wikipedia.org/wiki/Memory_refresh#DRAM