Crusoe Processor Ppt w614u
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INTRODUCTION CRUSOE PROCESSOR FAMILY MULTIPLE ISSUE MICROPROCESSORS VLIW APPROACH CODE MORPHING CRUSOE’S KEY PERFORMANCE OF CRUSOE PROCESSOR CONCLUSION REFERENCES
Crusoe processor is 128 bit microprocessor which is build for mobile computing devices where low power consumption is required. • VLIW based processor and x86 Code Morphing software provide x86-compatible mobile platform solution. • Processor core operates at 500-700 MHz.
TM TM TM TM
5400:-500-700 5500:-667-800 5600:-500-700 5800:-667-800
mhz. mhz mhz mhz
256k L2 cache 256k L2 cache 512k L2 cache 512K L2 cache
Several Functional Units (Integer ALUs, Floating Point Unit, Load/Store…) Multiple instructions issued per cycle Requires higher memory bandwidth and more s Two main flavors: Superscalar and VLIW.
Very Long Instruction Word processor Multiple FU’s, each explicitly programmed on each instruction A Very Long Instruction Word is called a molecule Each molecule contains 4 atoms: one instruction for each FU. A molecule is either 128 bits or 64 bits wide.
x86 instructions are converted to the Crusoe instruction set through a software layer During instruction translation, optimizations and scheduling tricks can be performed Crusoe Processor Architecture is decoupled from application software
x86 Applications x86 OS/BIOS Code Morphing Software
VLIW Processor Core
Code Morphing software resides in ROM Translations are performed dynamically and are cached Successively aggressive optimizations are performed each time a block is executed
x86 exceptions are precise (Problematic for out-of-order execution of instructions) On an exception, processor state is rolled back to the most recent commit. Execution proceeds in in-order mode until the fault location is found
Typical Approach 1: Switch off processor quickly to save power (Can give glitches) Typical Approach 2: Change clock rate by suspending processor and restarting Crusoe 1: Adjust clock rate dynamically, without suspension Crusoe 2: Adjust voltage level Result: Cubic power reduction, up to 30%.
The heatsink on the TM5400 Crusoe processor is quite small. • Execution Time – Comparable to direct hardware implementation by Intel or AMD
Transmeta has built an x86 Crusoe processor based on VLIW technology Code Morphing offers a new approach to the implementation of an instruction set architecture Crusoe offers the power of a highperformance Intel processor, consuming a fraction of the power
DOUGLAS V HALL: Microprocessors
and interfacing A.K.RAY and BHURCHANDI:
Advanced microprocessors and pheripherals
INTRODUCTION CRUSOE PROCESSOR FAMILY MULTIPLE ISSUE MICROPROCESSORS VLIW APPROACH CODE MORPHING CRUSOE’S KEY PERFORMANCE OF CRUSOE PROCESSOR CONCLUSION REFERENCES
Crusoe processor is 128 bit microprocessor which is build for mobile computing devices where low power consumption is required. • VLIW based processor and x86 Code Morphing software provide x86-compatible mobile platform solution. • Processor core operates at 500-700 MHz.
TM TM TM TM
5400:-500-700 5500:-667-800 5600:-500-700 5800:-667-800
mhz. mhz mhz mhz
256k L2 cache 256k L2 cache 512k L2 cache 512K L2 cache
Several Functional Units (Integer ALUs, Floating Point Unit, Load/Store…) Multiple instructions issued per cycle Requires higher memory bandwidth and more s Two main flavors: Superscalar and VLIW.
Very Long Instruction Word processor Multiple FU’s, each explicitly programmed on each instruction A Very Long Instruction Word is called a molecule Each molecule contains 4 atoms: one instruction for each FU. A molecule is either 128 bits or 64 bits wide.
x86 instructions are converted to the Crusoe instruction set through a software layer During instruction translation, optimizations and scheduling tricks can be performed Crusoe Processor Architecture is decoupled from application software
x86 Applications x86 OS/BIOS Code Morphing Software
VLIW Processor Core
Code Morphing software resides in ROM Translations are performed dynamically and are cached Successively aggressive optimizations are performed each time a block is executed
x86 exceptions are precise (Problematic for out-of-order execution of instructions) On an exception, processor state is rolled back to the most recent commit. Execution proceeds in in-order mode until the fault location is found
Typical Approach 1: Switch off processor quickly to save power (Can give glitches) Typical Approach 2: Change clock rate by suspending processor and restarting Crusoe 1: Adjust clock rate dynamically, without suspension Crusoe 2: Adjust voltage level Result: Cubic power reduction, up to 30%.
The heatsink on the TM5400 Crusoe processor is quite small. • Execution Time – Comparable to direct hardware implementation by Intel or AMD
Transmeta has built an x86 Crusoe processor based on VLIW technology Code Morphing offers a new approach to the implementation of an instruction set architecture Crusoe offers the power of a highperformance Intel processor, consuming a fraction of the power
DOUGLAS V HALL: Microprocessors
and interfacing A.K.RAY and BHURCHANDI:
Advanced microprocessors and pheripherals
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