Asynchronous Chip 2h45k

A Presentation On ASYNCHRONOUS CHIP

Guided By:-

Presented By:-

Mr. VIKAS TIWARI H.O.D.(E.C.E. Dept.)

SHEKHAR SHARMA EC Branch IV yr.

SIDDHI VINAYAK COLLEGE OF Sc. & Hr. EDUCATION ALWAR 1

Presentation flow:  Introduction.  Problems

with synchronous circuits.  Clockless / Asynchronous circuits.  How clockless chips work?  Simplicity in design.  Applications.  Applications (technical perspective).  Challenges. Presentation on Clockless Chips

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Introduction.  Struggle

for the improvement in the microprocessor’s

performance/functioning. – Pipelining – (Simultaneous) Multi-threading

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Synchronous

– Clockless / Asynchronous logic

Presentation on Clockless Chips

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Problems with Synchronous Approach  Distributing

the clock globally.

 Wastage

of energy.

 Traverse

the chip’s longest wires in one clock cycle.

 Order

of arrival of the signals is unimportant.

 Clocks

themselves consume lot of energy (~30%).

Presentation on Clockless Chips

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Synchronous circuit 

Longest path determines the minimum clock period.



Dissipation of energy for each clock cycle.



EMI is more in synchronous elements. Presentation on Clockless Chips

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Clockless chips (Asynchronous logic circuits)  Colckless

chips/Asynchronous/self-timed circuits.

 Functions

away from the clock.

 Different

parts work at different speeds.

 Hand-off the

result immediately.

Presentation on Clockless Chips

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Clock time cycle vs. clockless time cycle

Courtesy: Fulcrum Microsystems. Presentation on Clockless Chips

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Courtesy: Computers without clocks – Ivan E Sutherland and Jo Ebergen Presentation on Clockless Chips

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How do they work?  No

pure asynchronous chips are available.

 Uses

handshake signals for the data exchange.

 Data

moves only when required, not always.

– Minimizes power consumption. – Less EMI  less noise  more applications. – Stream data applications. Presentation on Clockless Chips

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Simple and efficient design  No

centralized clock required.

 Standardized

components can be used.

Presentation on Clockless Chips

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Some features  Integrated

pipelining mode.

– Domino logic. – Delay – insensitive.  Two

different implementation details

– Dual rail. – Bundled data. Presentation on Clockless Chips

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Advantages  Works

at its average speed.  Low power consumption.  Twice life-time.  Less

heat generated.

 Good to mobile devices.

EMI  less noise  more applications.  Smart cards (due to asynchronous nature).  Less

Presentation on Clockless Chips

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Advantages (technical look)  Asynchronous

for higher

performance: – Data-dependent delays. – All carry bits need to be computed.

Presentation on Clockless Chips

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Advantages (technical look)… 

Asynchronous for low power: – Consumes power only when and where active. – Rest of the time returns to a non-dissipating state, until next activation. – Illustrated through frequency divider Presentation on Clockless Chips

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Advantages (technical look)…  Asynchronous

for low power:

– Almost fixed power dissipation is achieved. – Many applications such as: • Infrared communication receiver. • Filter bank for digital hearing. • In pagers. • Double battery life. Presentation on Clockless Chips

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Advantages (technical look)…  Asynchronous

for low noise and low emission:

– Digital sub-circuits • Generates voltage noise (on power lines) • Induces current on silicon substrate. • Emits electromagnetic radiation at its clock frequency or its harmonics.

Presentation on Clockless Chips

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Advantages (technical look)… 

Heterogeneous Timing: – Gate delays. – Interconnection delays. – Heterogeneous systems would increase the delays in the circuits.

Presentation on Clockless Chips

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Challenges  Interfacing

between synchronous and asynchronous – Many devices available now are synchronous in nature. – Special circuits are needed to align them.

 Lack

of expertise.  Lack of tools.  Engineers are not trained in these fields.  Academically, no courses available. Presentation on Clockless Chips

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Thank you

Presentation on Clockless Chips

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